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| september 2011 doc id 022152 rev 1 1/154 1 stm32f405xx STM32F407XX arm cortex-m4 32b mcu+fpu, 210d mips, up to 1mb flash/192+4kb ram, usb otg hs/fs, ethernet, 17 tims, 3 adcs, 15 comm. interfaces & camera features core: arm 32-bit co rtex?-m4f cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0-wait state execution from flash memory, frequency up to 168 mhz, memory protection unit, 210 dmips/ 1.25 dmips/mhz (dhrystone 2.1), and dsp instructions memories ? up to 1 mbyte of flash memory ? up to 192+4 kbytes of sram including 64- kbyte of ccm (core coupled memory) data ram ? flexible static memory controller supporting compact flash, sram, psram, nor and nand memories lcd parallel interface, 8080/6800 modes clock, reset and supply management ? 1.8 v to 3.6 v application supply and i/os ? por, pdr, pvd and bor ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc (1% accuracy) ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc, 2032 bit backup registers + optional 4 kb backup sram 312-bit, 2.4 msps a/d co nverters: up to 24 channels and 7.2 msps in triple interleaved mode 212-bit d/a converters general-purpose dma: 16-stream dma controller with fifos and burst support up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 mhz, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input debug mode ? serial wire debug (swd) & jtag interfaces ? cortex-m4f embedded trace macrocell? up to 140 i/o ports with interrupt capability ? up to 136 fast i/os up to 84 mhz ? up to 138 5 v-tolerant i/os up to 15 communication interfaces ? up to 3 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts/2 uarts (10.5 mbit/s, iso 7816 interface, lin, irda, modem control) ? up to 3 spis (37.5 mbits/s), 2 with muxed full-duplex i 2 s to achieve audio class accuracy via internal audio pll or external clock ? 2 can interfaces (2.0b active) ? sdio interface advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full-speed phy and ulpi ? 10/100 ethernet mac with dedicated dma: supports ieee 1588v2 hardware, mii/rmii 8- to 14-bit parallel camera interface up to 54 mbytes/s analog random number generator crc calculation unit, 96-bit unique id rtc: subsecond accuracy, hardware calendar table 1. device summary reference part number stm32f405xx stm32f405rg, stm32f405vg, stm32f405zg STM32F407XX stm32f407vg, stm32f407ig, stm32f407zg, stm32f407ve, stm32f407ze, stm32f407ie lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp144 (20 20 mm) fbga ufbga176 (10 10 mm) lqfp176 (24 24 mm) www.st.com
contents stm32f405xx, STM32F407XX 2/154 doc id 022152 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.1 arm ? cortex?-m4f core with embedded flash and sram . . . . . . . . 17 2.2.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . 17 2.2.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 18 2.2.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.9 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.10 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 20 2.2.11 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.12 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.13 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.14 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.15 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.16 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.17 real-time clock (rtc), backup sram and backup registers . . . . . . . . 25 2.2.18 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.19 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.20 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.21 inter-integrated circuit interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.22 universal synchronous/asynchronous receiver transmitters (usart) . 30 2.2.23 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.24 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.25 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.26 secure digital input/output interface (sdio) . . . . . . . . . . . . . . . . . . . . . 32 2.2.27 ethernet mac interface with dedicated dma and ieee 1588 support . 32 2.2.28 controller area network (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.29 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . 34 stm32f405xx, STM32F407XX contents doc id 022152 rev 1 3/154 2.2.30 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . 34 2.2.31 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.32 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.33 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.34 analog-to-digital converters (adcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.35 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.36 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.37 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.38 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.2 vcap1/vcap2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.3 operating conditions at power-up / power-down (regulator on) . . . . . . 61 5.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 61 5.3.5 embedded reset and power control block characteristics . . . . . . . . . . . 62 5.3.6 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.7 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.3.8 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.9 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.10 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.11 pll spread spectrum clock generation (sscg) characteristics . . . . . . 81 5.3.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 contents stm32f405xx, STM32F407XX 4/154 doc id 022152 rev 1 5.3.13 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.14 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 86 5.3.15 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.3.16 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3.17 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.18 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.20 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.3.21 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3.22 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3.23 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3.24 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.25 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.3.26 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 135 5.3.27 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 135 5.3.28 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 appendix a application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 a.1 main applications versus package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 a.2 application example with regulator off . . . . . . . . . . . . . . . . . . . . . . . . . 146 a.3 usb otg full speed (fs) interface solutions . . . . . . . . . . . . . . . . . . . . . 147 a.4 usb otg high speed (hs) interface solutions . . . . . . . . . . . . . . . . . . . . 148 a.5 complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 stm32f405xx, STM32F407XX list of tables doc id 022152 rev 1 5/154 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f405xx and STM32F407XX: features and peripheral counts. . . . . . . . . . . . . . . . . . 11 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 4. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5. stm32f40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 6. alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 7. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 8. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 9. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 10. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 11. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 60 table 12. vcap1/vcap2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 13. operating conditions at power-up / power-down (regulator on) . . . . . . . . . . . . . . . . . . . . 61 table 14. operating conditions at power-up / power-down (regulator off). . . . . . . . . . . . . . . . . . . . 61 table 15. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 16. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 17. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram . . . . . . . . . . . . . . . . . . . 65 table 18. typical and maximum current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 66 table 19. typical and maximum current consumptions in stop mode . . . . . . . . . . . . . . . . . . . . . . . . 67 table 20. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 67 table 21. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . . 68 table 22. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 23. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 24. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 25. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 26. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 27. hse 4-26 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 table 28. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 29. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 30. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 31. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 32. plli2s (audio pll) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 33. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 34. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 35. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 36. flash memory programming with v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 37. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 38. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 39. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 40. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 41. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 42. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 43. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 44. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 45. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 46. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 list of tables stm32f405xx, STM32F407XX 6/154 doc id 022152 rev 1 table 47. characteristics of timx connected to the apb1 domain . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 48. characteristics of timx connected to the apb2 domain . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 49. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 50. scl frequency (f pclk1 = 42 mhz.,v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 51. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 52. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 53. usb otg fs startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 54. usb otg fs dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 55. usb otg fs electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 56. usb fs clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 03 table 57. usb hs dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 table 58. usb hs clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 table 59. ulpi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 60. ethernet dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 61. dynamics characteristics: ethernet mac signals for smi. . . . . . . . . . . . . . . . . . . . . . . . . 105 table 62. dynamics characteristics: ethernet mac signals for rmii . . . . . . . . . . . . . . . . . . . . . . . . 106 table 63. dynamics characteristics: ethernet mac signals for mii . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 64. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 65. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 66. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 67. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 68. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 69. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 70. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . 116 table 71. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 117 table 72. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 73. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 74. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 75. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 76. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . 125 table 77. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 78. switching characteristics for pc card/cf read and write cycles . . . . . . . . . . . . . . . . . . . 131 table 79. switching characteristics for nand flash read and write cycles . . . . . . . . . . . . . . . . . . . 134 table 80. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 81. sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 82. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 83. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 138 table 84. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 139 table 85. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 140 table 86. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data . 141 table 87. lqfp176, 24 x 24 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 142 table 88. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 89. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 90. main applications versus package for STM32F407XX microcontrollers . . . . . . . . . . . . . . 145 table 91. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 stm32f405xx, STM32F407XX list of figures doc id 022152 rev 1 7/154 list of figures figure 1. compatible board design between stm32f2xx and stm32f4xx: lqfp176 . . . . . . . . . . 13 figure 2. compatible board design between stm32f1xx/stm32f2xx/ . . . . . . . . . . . . . . . . . . . . . . . . stm32f4xx: lqfp144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. compatible board design stm32f1xx/stm32f2xx/ stm32f4xx: lqfp100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. compatible board design between stm32f1xx/stm32f4xx: lqfp64 . . . . . . . . . . . . . . . 15 figure 5. stm32f40x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. regulator on/internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. stm32f40x lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. stm32f40x lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. stm32f40x lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 13. stm32f40x lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 14. stm32f40x ufbga176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 figure 15. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 16. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 17. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 18. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 19. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 20. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 21. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 22. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 23. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 24. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 25. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 26. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 27. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 28. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 29. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 30. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 31. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 32. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 33. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 34. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 35. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 36. usb otg fs timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 103 figure 37. ulpi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 38. ethernet smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 39. ethernet rmii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 40. ethernet mii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 41. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 42. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 43. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 111 figure 44. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 111 list of figures stm32f405xx, STM32F407XX 8/154 doc id 022152 rev 1 figure 45. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 46. asynchronous non-multiplexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 116 figure 47. asynchronous non-multiplexed sram/psram/nor write waveforms . . . . . . . . . . . . . . 117 figure 48. asynchronous multiplexed psram/nor read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 118 figure 49. asynchronous multiplexed psram/nor write waveforms . . . . . . . . . . . . . . . . . . . . . . . 120 figure 50. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 51. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 52. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 53. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 54. pc card/compactflash controller waveforms for common memory read access . . . . . . 127 figure 55. pc card/compactflash controller waveforms for common memory write access . . . . . . 128 figure 56. pc card/compactflash controlle r waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 57. pc card/compactflash controlle r waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 58. pc card/compactflash controller waveforms for i/o space read access . . . . . . . . . . . . 130 figure 59. pc card/compactflash controller waveforms for i/o space write access . . . . . . . . . . . . 131 figure 60. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 61. nand controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 62. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 134 figure 63. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 134 figure 64. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 65. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 66. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 138 figure 67. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 68. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 139 figure 69. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 70. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 71. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 72. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline . 141 figure 73. lqfp176 24 x 24 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 142 figure 74. regulator off/internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 75. regulator off/internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 76. usb otg fs peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 77. usb otg fs host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 78. otg fs connection dual-role with internal phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 79. usb otg hs peripheral-only connection in fs mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 80. usb otg hs host-only connection in fs mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 81. otg hs connection dual-role with external phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 82. complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 83. complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 84. audio player solution using pll, plli2s, usb and 1 crystal . . . . . . . . . . . . . . . . . . . . . . 151 figure 85. audio pll (plli2s) providing accurate i2s clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 86. master clock (mck) used to drive the external audio dac. . . . . . . . . . . . . . . . . . . . . . . . 152 figure 87. master clock (mck) not used to drive the external audio dac. . . . . . . . . . . . . . . . . . . . . 152 stm32f405xx, STM32F407XX introduction doc id 022152 rev 1 9/154 1 introduction this datasheet provides the description of the stm32f405xx and STM32F407XX lines of microcontrollers. for more details on the whole stmicroelectronics stm32? family, please refer to section 2.1: full compatib ility throughout the family . the stm32f405xx and STM32F407XX datasheet should be read in conjunction with the stm32f4xx reference manual. for information on programming, erasing and protection of the internal flash memory, please refer to the stm32f4xx flash programming manual (pm0081). the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com . for information on the cortex?-m4f core please refer to the cortex?-m4f technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/. description stm32f405xx, STM32F407XX 10/154 doc id 022152 rev 1 2 description the stm32f405xx and STM32F407XX family is based on the high-performance arm ? cortex?-m4f 32-bit risc core operating at a frequency of up to 168 mhz. the cortex-m4f core features a floating point unit (fpu) sing le precision which supports all arm single- precision data-processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (mpu) which enhances application security. the stm32f405xx and STM32F407XX family incorporates high-speed embedded memories (flash memory up to 1 mbyte, up to 192 kbytes of sram), up to 4 kbytes of backup sram, and an extensive range of enhanced i/os and peripherals connected to two apb buses, two ahb buses and a 32-bit multi-ahb bus matrix. all devices offer three 12-bit adcs, two dacs, a low-power rtc, twelve general-purpose 16-bit timers including two pwm timers for motor control, two general-purpose 32-bit timers. a true number random generator (rng). they also feature standard and advanced communication interfaces. up to three i 2 cs three spis, two i 2 ss full duplex. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external clock to allow synchronization. four usarts plus two uarts an usb otg full-speed and a usb otg high- speed with full-speed capability (with the ulpi), tw o c a n s an sdio/mmc interface ethernet and the camera interface available on STM32F407XX devices only. new advanced peripherals include an sdio, an enhanced flexible static memory control (fsmc) interface (for devices offered in packages of 100 pins and more), a camera interface for cmos sensors. refer to table 2: stm32f405xx and STM32F407XX: features and peripheral counts for the list of peripherals available on each part number. the stm32f405xx and STM32F407XX family operates in the ?40 to +105 c temperature range from a 1.8 to 3.6 v power supply. the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range and pdr_on is connected to v ss . a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f405xx and STM32F407XX family offers devices in four packages ranging from 64 pins to 176 pins. the set of included peripherals changes with the device chosen. these features make the stm32f405xx and STM32F407XX microcontroller family suitable for a wide range of applications: motor drive and application control medical equipment industrial applications: plc, inverters, circuit breakers printers, and scanners alarm systems, video intercom, and hvac home audio appliances figure 5 shows the general block diagram of the device family. stm32f405xx, STM32F407XX description doc id 022152 rev 1 11/154 table 2. stm32f405xx and STM32F407XX: features and peripheral counts peripherals stm32f405rg stm32f405vg stm32f40 5zg stm32f407vx stm32f407zx stm32f407ix flash memory in kbytes 1024 512 1024 512 1024 512 1024 sram in kbytes system 192(112+16+64) backup 4 fsmc memory controller no yes ethernet no yes timers general-purpose 10 advanced- control 2 basic 2 random number generator yes communication interfaces spi / i 2 s 3/2 (full duplex) i 2 c 3 usart/uart 4/2 usb otg fs yes usb otg hs yes can 2 camera interface no yes gpios 51 82 114 82 114 140 12-bit adc number of channels 3 16 16 24 16 24 24 12-bit dac number of channels ye s 2 maximum cpu frequency 168 mhz operating voltage 1.8 to 3.6 v (1) description stm32f405xx, STM32F407XX 12/154 doc id 022152 rev 1 operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c package lqfp64 lqfp100 lqfp144 lqfp100 lqfp144 ufbga176 lqfp176 1. v dd minimum value of 1.7 v is obtained when the device operates in the 0 to 70 c temperature range and pdr_on is connected to v ss . table 2. stm32f405xx and STM32F407XX: features and peripheral counts (continued) peripherals stm32f405rg stm32f405vg stm32f40 5zg stm32f407vx stm32f407zx stm32f407ix stm32f405xx, STM32F407XX description doc id 022152 rev 1 13/154 2.1 full compatibility throughout the family the stm32f405xx and STM32F407XX are part of the stm32f4 family. they are fully pin- to-pin, software and feature compatible with the stm32f2xx devices, allowing the user to try different memory densities, peripherals, and performances (fpu, higher frequency) for a greater degree of freedom during the development cycle. the stm32f405xx and stm32f 407xx devices maintain a close compatibility with the whole stm32f10xxx family. all functional pins are pin-to-pin compatible. the stm32f405xx and STM32F407XX, however, are not drop-in replacements for the stm32f10xxx devices: the two families do not have the same power scheme, and so their power pins are different. nonetheless, transition from the stm32f10xxx to the stm32f40x family remains simple as only a few pins are impacted. figure 1 , figure 2 , figure 3 , and figure 4 give compatible board designs between the stm32f40x, stm32f2xxx, and stm32f10xxx families. figure 1. compatible board design between stm32f2xx and stm32f4xx: lqfp176 1. by default, pdr_on (pin 171) should be connected to v dd . 2. pin 171 is rfu for stm32f2xx. 4 w o r e s i s t o r s c o n n e c t e d t o 6 3 3 6 $ $ o r . # f o r t h e 3 4 - & x x 6 $ $ o r 6 3 3 f o r t h e 3 4 - & x x x x - 3 6 0 $ 2 ? / . 6 3 3 6 $ $ description stm32f405xx, STM32F407XX 14/154 doc id 022152 rev 1 figure 2. compatible board design between stm32f1xx/stm32f2xx/ stm32f4xx: lqfp144 1. by default, pdr_on (pin 143) should be connected to v dd . 2. pin 143 is rfu for stm32f2xx. figure 3. compatible board design stm32f1xx/stm32f2xx/ stm32f4xx: lqfp100 1. by default, pdr_on (pin 99) should be connected to v dd . 2. pin 99 is rfu for stm32f2xx. 6 3 3 r e s i s t o r o r s o l d e r i n g b r i d g e p r e s e n t f o r t h e 3 4 - & x x x c o n f i g u r a t i o n n o t p r e s e n t i n t h e 3 4 - & x x x x c o n f i g u r a t i o n 6 3 3 4 w o r e s i s t o r s c o n n e c t e d t o 6 3 3 f o r t h e 3 4 - & x x x 6 $ $ o r 6 3 3 f o r t h e 3 4 - & x x x x 6 3 3 6 $ $ 6 3 3 6 3 3 a i b 0 $ 2 ? / . 6 3 3 6 $ $ 6 3 3 f o r 3 4 - & x x x 6 $ $ f o r 3 4 - & x x x x 6 3 3 6 $ $ o r . # f o r t h e 3 4 - & x x 6 3 3 6 3 3 6 $ $ 6 3 3 6 3 3 6 3 3 a r e s i s t o r o r s o l d e r i n g b r i d g e p r e s e n t f o r t h e 3 4 - & x x x c o n f i g u r a t i o n n o t p r e s e n t i n t h e 3 4 - & x x x x c o n f i g u r a t i o n a i b 0 $ 2 ? / . 6 3 3 6 $ $ 4 w o r e s i s t o r s c o n n e c t e d t o 6 3 3 f o r t h e 3 4 - & x x x 6 $ $ o r 6 3 3 f o r t h e 3 4 - & x x x x 6 3 3 f o r 3 4 - & x x x 6 $ $ f o r 3 4 - & x x x x 6 3 3 6 $ $ o r . # f o r t h e 3 4 - & x x stm32f405xx, STM32F407XX description doc id 022152 rev 1 15/154 figure 4. compatible board design between stm32f1xx/stm32f4xx: lqfp64 6 3 3 6 3 3 6 3 3 6 3 3 r e s i s t o r o r s o l d e r i n g b r i d g e p r e s e n t f o r t h e 3 4 - & x x x c o n f i g u r a t i o n n o t p r e s e n t i n t h e 3 4 - & x x x x c o n f i g u r a t i o n a i description stm32f405xx, STM32F407XX 16/154 doc id 022152 rev 1 2.2 device overview figure 5. stm32f40x block diagram 1. the timers connected to apb2 are clocked from timxclk up to 168 mhz, while the timers connected to apb1 are clocked from timxclk up to 84 mhz. ' 0 ) / 0 / 2 4 ! ! ( " ! 0 " % 8 4 ) 4 7 + 5 0 ! & 0 ! ; = ' 0 ) / 0 / 2 4 " 0 " ; = 4 ) - 0 7 - c o m p l c h a n n e l s 4 ) - ? # ( ; = . c h a n n e l s 4 ) - ? # ( ; = % 4 2 " + ) . a s ! & 4 ) - 0 7 - ' 0 ) / 0 / 2 4 # 0 # ; = 5 3 ! 2 4 2 8 4 8 # + # 4 3 2 4 3 a s ! & ' 0 ) / 0 / 2 4 $ 0 $ ; = ' 0 ) / 0 / 2 4 % 0 % ; = ' 0 ) / 0 / 2 4 & 0 & ; = ' 0 ) / 0 / 2 4 ' 0 ' ; = 3 0 ) - / 3 ) - ) 3 / 3 # + . 3 3 a s ! & ! 0 " - ( z ! 0 " - ( z a n a l o g i n p u t s c o m m o n t o t h e ! $ # s a n a l o g i n p u t s c o m m o n t o t h e ! $ # 6 $ $ 2 % & ? ! $ # a n a l o g i n p u t s t o ! $ # c h a n n e l s % 4 2 a s ! & c h a n n e l s % 4 2 a s ! & c h a n n e l s % 4 2 a s ! & c h a n n e l s % 4 2 a s ! & 2 8 4 8 # + 5 3 ! 2 4 2 8 4 8 # + 5 3 ! 2 4 2 8 4 8 a s ! & 5 ! 2 4 2 8 4 8 a s ! & 5 ! 2 4 - / 3 ) 3 $ - ) 3 / 3 $ ? e x t 3 # + # + 3 0 ) ) 3 . 3 3 7 3 - # + a s ! & - / 3 ) 3 $ - ) 3 / 3 $ ? e x t 3 # + # + 3 0 ) ) 3 . 3 3 7 3 - # + a s ! & 3 # , 3 $ ! 3 - " ! a s ! & ) # 3 - " 5 3 3 # , 3 $ ! 3 - " ! a s ! & ) # 3 - " 5 3 4 8 2 8 b x # ! . 4 8 2 8 b x # ! . $ ! # ? / 5 4 a s ! & $ ! # ? / 5 4 a s ! & ) 4 & 7 7 $ ' + " " + 0 3 2 ! - 2 4 # ? ! & / 3 # ? ) . / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? / 5 4 . 2 3 4 6 $ $ ! 6 3 3 ! 6 # ! 0 6 # ! 0 5 3 ! 2 4 2 8 4 8 # + # 4 3 2 4 3 a s ! & s m c a r d i r $ ! s m c a r d i r $ ! s m c a r d i r $ ! s m c a r d i r $ ! b b b b b b b b # 4 3 2 4 3 a s ! & # 4 3 2 4 3 a s ! & 3 $ ) / - - # $ ; = # - $ # + a s ! & 6 " ! 4 t o 6 $ - ! ! ( " ! 0 " $ - ! 3 # , 3 $ ! 3 - " ! a s ! & ) # 3 - " 5 3 ' 0 ) / 0 / 2 4 ( 0 ( ; = ' 0 ) / 0 / 2 4 ) 0 ) ; = * 4 ! ' 3 7 ! 2 - # o r t e x - & - ( z 3 " 5 3 ) " 5 3 . 6 ) # % 4 - - 0 5 . * 4 2 3 4 * 4 $ ) * 4 $ / 3 7 $ * 4 $ / 4 2 ! # % # , + 4 2 ! # % $ ; = * 4 # + 3 7 # , + % t h e r n e t - ! # $ - ! - ) ) o r 2 - ) ) a s ! & - $ ) / a s ! & & ) & / 5 3 " $ - ! & ) & / / 4 ' ( 3 $ 0 $ - 5 , 0 ) # + $ $ ) 2 3 4 0 . 8 4 $ - ! 3 t r e a m s & ) & / $ - ! 3 t r e a m s & ) & / ! 2 4 ! # # % , # ! # ( % 3 2 ! - + " # , + . % ; = ! ; = $ ; = / % . 7 % . . " , ; = . , . 2 % ' . 7 ! ) 4 ) / 2 $ 9 # $ . ) / 2 $ ) / 7 2 ) . 4 ; = ) . 4 . . ) ) 3 a s ! & 3 # , 3 $ ! ) . 4 . ) $ 6 " 5 3 3 / & 2 . ' # a m e r a i n t e r f a c e ( 3 9 . # 6 3 9 . # 0 ) 8 # , + $ ; = 5 3 " 0 ( 9 / 4 ' & 3 $ 0 $ - & ) & / & ) & / ! ( ( " - ( z 0 ( 9 & ) & / 5 3 ! 2 4 - " p s 4 e m p e r a t u r e s e n s o r ! $ # ! $ # ! $ # ) & ) & 6 $ $ ! 6 $ $ ! 0 / 2 0 $ 2 3 u p p l y 6 $ $ ! s u p e r v i s i o n 0 6 $ 2 e s e t ) n t 0 / 2 8 4 ! , / 3 # - ( z 8 4 ! , k ( z ( # , + x - ! . ! ' 4 2 4 # 2 # ( 3 & # , + 2 # , 3 3 t a n d b y ) 7 $ ' 6 " ! 4 6 $ $ ! 6 $ $ ! 7 5 2 e s e t c l o c k c o n t r o l 0 , , 0 # , + x i n t e r f a c e 6 $ $ t o 6 6 3 3 6 o l t a g e r e g u l a t o r 6 t o 6 6 $ $ 0 o w e r m a n a g m t 6 $ $ 2 4 # ? ! & " a c k u p r e g i s t e r 3 # , 3 $ ! ) . 4 . ) $ 6 " 5 3 3 / & ! ( " b u s m a t r i x 3 - ! 0 " - ( z , 3 , 3 c h a n n e l s a s ! & c h a n n e l a s ! & c h a n n e l a s ! & 4 ) - b b b 4 ) - c h a n n e l s a s ! & 4 ) - c h a n n e l a s ! & b b 4 ) - c h a n n e l a s ! & b " / 2 $ ! # $ ! # & l a s h u p t o - " 3 2 ! - 0 3 2 ! - . / 2 & l a s h 0 # # a r d ! 4 ! . ! . $ & l a s h % x t e r n a l m e m o r y c o n t r o l l e r & 3 - # 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - $ " 5 3 - 3 6 c o m p l c h a n n e l s 4 ) - ? # ( ; = . c h a n n e l s 4 ) - ? # ( ; = % 4 2 " + ) . a s ! & & ) & / & 0 5 ! 0 " - ( z m a x 3 2 ! - + " # # - d a t a 2 ! - + " ! ( " ! ( " - ( z stm32f405xx, STM32F407XX description doc id 022152 rev 1 17/154 2.2.1 arm ? cortex?-m4f core with embedded flash and sram the arm cortex-m4f processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm cortex-m4f 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructi ons which allow efficient signal processing and complex algorithm execution. its single precision fpu (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. the stm32f405xx and STM32F407XX family is compatible with all arm tools and software. figure 5 shows the general block diagram of the stm32f40x family. note: cortex-m4f is binary compatible with cortex-m3. 2.2.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelera tor which is optimized for stm32 industry- standard arm ? cortex?-m4f processors. it balances the inherent performance advantage of the arm cortex-m4f over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor full 210 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accelerator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 168 mhz. 2.2.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful fo r applications where some critic al or certified code has to be protected against the misbehavior of other tasks. it is usually managed by an rtos (real- time operating system). if a program accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. 2.2.4 embedded flash memory the stm32f40x devices embed a flash memory of 256 kbytes, 512 kbytes, 768 kbytes or 1 mbytes available for storing programs and data. description stm32f405xx, STM32F407XX 18/154 doc id 022152 rev 1 2.2.5 crc (cyclic redundanc y check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 embedded sram all stm32f40x products embed: up to 192 kbytes of system sram includin g 64 kbytes of ccm (core coupled memory) data ram ram memory is accessed (read/write) at cpu clock speed with 0 wait states. 4 kbytes of backup sram this area is accessible only from the cp u. its content is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 2.2.7 multi-ahb bus matrix the 32-bit multi-ahb bus matrix interconnects all the masters (cpu, dmas, ethernet, usb hs) and the slaves (flash memory, ram, fsmc, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. stm32f405xx, STM32F407XX description doc id 022152 rev 1 19/154 figure 6. multi-ahb matrix 2.2.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral tr ansfers. they feature dedicate d fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. ! 2 - # o r t e x - & ' 0 $ - ! ' 0 $ - ! - ! # % t h e r n e t 5 3 " / 4 ' ( 3 " u s m a t r i x 3 3 3 3 3 3 3 3 3 ) # / $ % $ # / $ % ! # # % , & l a s h m e m o r y 3 2 ! - + b y t e 3 2 ! - + b y t e ! ( " p e r i p h ! ( " p e r i p h & 3 - # 3 t a t i c - e m # t l - - - - - - - ) b u s $ b u s 3 b u s $ - ! ? 0 ) $ - ! ? - % - $ - ! ? - % - $ - ! ? 0 % 4 ( % 2 . % 4 ? - 5 3 " ? ( 3 ? - a i # # - d a t a 2 ! - + b y t e ! 0 " ! 0 " description stm32f405xx, STM32F407XX 20/154 doc id 022152 rev 1 the dma can be used with the main peripherals: spi and i 2 s i 2 c usart general-purpose, basic and advanced-control timers timx dac sdio camera interface (dcmi) adc. 2.2.9 flexible static memory controller (fsmc) the fsmc is embedded in the stm32f405xx and STM32F407XX family. it has four chip select outputs supporting the following modes: pccard/compact flash, sram, psram, nor flash and nand flash. functionality overview: write fifo maximum frequency (f clk ) for external access is 60 mhz. lcd parallel interface the fsmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel interface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 nested vectored inte rrupt controller (nvic) the stm32f405xx and STM32F407XX embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 87 maskable interrupt channels plus the 16 interrupt lines of the cortex?-m4f. closely coupled nvic gives low-latency interrupt processing interrupt entry vector table address passed directly to the core allows early processing of interrupts processing of late arriving, higher-priority interrupts support tail chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 external interr upt/event controller (exti) the external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a stm32f405xx, STM32F407XX description doc id 022152 rev 1 21/154 pulse width shorter than the internal apb2 cloc k period. up to 140 gp ios can be connected to the 16 external interrupt lines. 2.2.12 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-trim med to offer 1% accuracy over the full temperature range. the application can then select the system clock between the rc oscillator and an external 4-26 mhz clock source . this clock can be monitored for failure. if a failure is detected, the system automatically sw itches back to the in ternal rc oscillator and a software interrupt is generated (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 168 mhz. similarly, full interrupt management of the pll clock entry is available when necessary (for example if an indirectly used external oscillator fails). several prescalers allow the configuration of the two ahb buses, the high-speed apb (apb2) and the low-speed apb (apb1) domains. the maximum frequency of the two ahb buses is 168 mhz while the maximum frequenc y of the high-speed apb domains is 84 mhz. the maximum allowed frequency of the low-speed apb domain is 42 mhz. the devices embed a dedicated pll (plli2s) which allows to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz. 2.2.13 boot modes at startup, boot pins are used to select one out of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10), usart3 (pc10/pc 11 or pb10/pb11), can2 (pb5/pb6), usb otg fs in device mode (pa9/pa11/pa12) through dfu (device firmware upgrade). 2.2.14 power supply schemes v dd = 1.8 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. v ssa , v dda = 1.8 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. refer to figure 18: power supply scheme for more details. note: v dd /v dda minimum value of 1.7 v is obtained when the device operates in the 0 to 70 c temperature range with pdr_on connected to v ss . description stm32f405xx, STM32F407XX 22/154 doc id 022152 rev 1 2.2.15 power supply supervisor the power supply supervisor is enabled by holding pdr_on high. the device has an integrated power-on reset (por) / power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitr y. at power-on, bor is always active, and ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. all packages, except the lqfp64, offer the internal reset is controlled through the pdr_on signal. 2.2.16 voltage regulator the regulator has eight operating modes: regulator on/internal reset on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down regulator on/internal reset off ? main regulator mode (mr) ? low power regulator (lpr) ? power-down regulator off/internal reset on regulator off/internal reset off regulator on regulator on/internal reset on the regulator on/internal reset on mode is always enabled on lqfp64 package. on lqfp100 and lqfp144 packages, this mode is activated by setting pdr_on to v dd . on ufbga176 package, the internal regulator must be activated by connecting bypass_reg to v ss, and pdr_on to v dd . on lqfp176 packages, the internal reset must be activated by connecting pdr_on to v dd . stm32f405xx, STM32F407XX description doc id 022152 rev 1 23/154 v dd minimum value is 1.8 v (a) . there are three low-power modes: ? mr is used in the nominal regulation mode (run) ? lpr is used in the stop modes ? power-down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, indu cing zero consumption (but the contents of the registers and sram are lost). regulator on/internal reset off the regulator on with internal reset off mode is not available on lqfp64 package. on lqfp100 and lqfp144 packages, the internal reset is controlled by setting pdr_on pin to v ss . on ufbga176 package, the internal regulator must be activated by connecting bypass_reg to v ss, and pdr_on to v ss . on lqfp176 packages, the internal reset must be activated by connecting pdr_on to v ss . the nrst pin should be controlled by an external reset controller to keep the device under reset when v dd is below 1.8 v (see figure 7 ). figure 7. regulator on/internal reset off a. v dd /v dda minimum value of 1.7 v is obtained when the device operates in the 0 to 70 c temperature range and pdr_on is connected to v ss . 6 $ $ t i m e - 3 6 0 $ 2 6 t i m e . 2 3 4 description stm32f405xx, STM32F407XX 24/154 doc id 022152 rev 1 regulator off this mode allows to power the device as soon as v dd reaches 1.8 v. regulator off/internal reset on this mode is available only on ufbga package. it is activated by setting bypass_reg and pdr_on pins to v dd . the regulator off/internal reset on mode allows to supply externally a 1.2 v voltage source through v cap_1 and v cap_2 pins, in addition to v dd . the following conditions must be respected: ?v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach 1.08 v is faster than the time for v dd to reach 1.8 v (a) , then pa0 should be connected to the nrst pin (see figure 8 ). otherwise, pa0 should be asserted low externally during por until v dd reaches 1.8 v (see figure 9 ). ?if v cap_1 and v cap_2 go below 1.08 v and v dd is higher than 1.7 v, then a reset must be asserted on pa0 pin. in regulator off/internal reset on mode, pa0 cannot be used as a gpio pin since it allows to reset the part of the 1.2 v logic which is not reset by the nrst pin, when the internal voltage regulator in off. regulator off/internal reset off this mode is available only on ufbga package. it is activated by setting bypass_reg pin to v dd and by applying an inverted reset signal to pdr_on, and allows to supply externally a 1.2 v voltage source through v cap_1 and v cap_2 pins, in addition to v dd . the following conditions must be respected: ?v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? pa0 should be kept low to cover both conditions: until v cap_1 and v cap_2 reach 1.08 v and until v dd reaches 1.8 v (see figure 8 ). ? nrst should be controlled by an external reset controller to keep the device under reset when v dd is below 1.8 v (see figure 9 ). stm32f405xx, STM32F407XX description doc id 022152 rev 1 25/154 figure 8. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid both whatever the internal reset mode (on or off). figure 9. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 1. this figure is valid both whatever the internal reset mode (on or off). 2.2.17 real-time clock (rtc), backup sram and backup registers the backup domain of the stm32f405xx and STM32F407XX includes: the real-time clock (rtc) 4 kbytes of backup sram 20 backup registers the real-time clock (rtc) is an independent bcd timer/counter. dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in bcd (binary-coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the sub-seconds value is also available in binary format. 6 $ $ t i m e 6 a i b 0 $ 2 6 6 # ! 0 ? 6 # ! 0 ? 6 t i m e 0 ! t i e d t o . 2 3 4 . 2 3 4 6 $ $ t i m e 6 0 $ 2 6 6 # ! 0 ? 6 # ! 0 ? 6 t i m e 0 ! a s s e r t e d e x t e r n a l l y . 2 3 4 description stm32f405xx, STM32F407XX 26/154 doc id 022152 rev 1 it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high -speed external clock divided by 128. the intern al low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. two alarm registers are used to generate an alar m at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base clock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the 4-kbyte backup sram is an eeprom-like memory area. it can be used to store data which need to be retained in vbat and standby mode. this memory area is disabled by default to minimize power consumption (see section 2.2.18: low-power modes ). it can be enabled by software. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 2.2.18: low-power modes ). additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. like backup sram, the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or from the v bat pin. 2.2.18 low-power modes the stm32f405xx and STM32F407XX support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from the stop mode by any of the exti line (the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup or the ethernet wakeup). standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering stm32f405xx, STM32F407XX description doc id 022152 rev 1 27/154 standby mode, the sram and register contents are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm / wakeup / tamper /time stamp event occurs. note: 1 when in standby mode, only an rtc alarm/event or an external reset can wake up the device provided v dd is supplied by an external battery. 2.2.19 v bat operation the v bat pin allows to power the device v bat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation. 2.2.20 timers and watchdogs the stm32f405xx and STM32F407XX devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode. ta bl e 3 compares the features of the advanced-control, general-purpose and basic timers. description stm32f405xx, STM32F407XX 28/154 doc id 022152 rev 1 advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: input capture output compare pwm generation (edge- or center-aligned modes) one-pulse mode output if configured as standard 16-bit timers, they have the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). the advanced-control timer can work together with the timx timers via the timer link feature for synchronization or event chaining. tim1 and tim8 support independent dma request generation. table 3. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary output max interface clock (mhz) max timer clock (mhz) advanced- control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s 8 4 1 6 8 general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 42 84 tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 42 84 tim9 16-bit up any integer between 1 and 65536 no 2 no 84 168 tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no 84 168 tim12 16-bit up any integer between 1 and 65536 no 2 no 42 84 tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no 42 84 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 42 84 stm32f405xx, STM32F407XX description doc id 022152 rev 1 29/154 general-purpose timers (timx) there are ten synchronizable general-purpose timers embedded in the stm32f40x devices (see ta b l e 3 for differences). tim2, tim3, tim4, tim5 the stm32f40x include 4 full-featured general-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they all feature 4 independent channels for input capture/output compare, pwm or one-pulse mode output. this gives up to 16 input capture/output compare/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers tim1 and tim8 via the timer link feature for synchr onization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have independent dma request generation. they are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. tim9, tim10, tim11, tim12, tim13, and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10, tim11, tim13, and tim14 feature one independent channel, whereas tim9 and tim12 have two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base. tim6 and tim7 support independent dma request generation. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. window watchdog the window watchdog is based on a 7-bit downc ounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. description stm32f405xx, STM32F407XX 30/154 doc id 022152 rev 1 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: a 24-bit downcounter autoreload capability maskable system interrupt generation when the counter reaches 0 programmable clock source. 2.2.21 inter-integrated circuit interface (i2c) up to three i2c bus interfaces can operate in multimaster and slave modes. they can support the standard- and fast-modes. they support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. 2.2.22 universal sync hronous/asynchronous receiver transmitters (usart) the stm32f405xx and STM32F407XX embed four universal synchronous/asynchronous receiver transmitters (usart1, usart2, usart3 and usart6) and two universal asynchronous receiver transm itters (uart4 and uart5). these six interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usar t1 and usart6 interf aces are able to communicate at speeds of up to 10.5 mbit/s. the other available interfaces communicate at up to 5.25 bit/s. usart1, usart2, usart3 and usart6 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like communication capability. all interfaces can be served by the dma controller. stm32f405xx, STM32F407XX description doc id 022152 rev 1 31/154 2.2.23 serial perip heral interface (spi) the stm32f40x feature up to three spis in slave and master modes in full-duplex and simplex communication modes. spi1 can communicate at up to 37.5 mbits/s, spi2 and spi3 can communicate at up to 21 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operate in ti mode for communications in master mode and slave mode. 2.2.24 inter-integrated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available. they can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency. all i 2 sx can be served by the dma controller. table 4. usart feature comparison usart name standard features modem (rts/cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s (oversampling by 16) max. baud rate in mbit/s (oversampling by 8) apb mapping usart1 x x x x x x 5.25 10.5 apb2 (max. 84 mhz) usart2 x x x x x x 2.62 5.25 apb1 (max. 42 mhz) usart3 x x x x x x 2.62 5.25 apb1 (max. 42 mhz) usart4 x - - - - - 2.62 5.25 apb1 (max. 42 mhz) usart5 x - - - - - 2.62 5.25 apb1 (max. 42 mhz) usart6 x x x x x x 5.25 10.5 apb2 (max. 84 mhz) description stm32f405xx, STM32F407XX 32/154 doc id 022152 rev 1 2.2.25 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s application. it allows to achieve error-free i 2 s sampling clock accuracy without compromising on the cpu performance, while using usb peripherals. the plli2s configuration can be modified to manage an i 2 s sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i2s flow with an external pll (or codec output). 2.2.26 secure digital i nput/output inte rface (sdio) an sd/sdio/mmc host interface is availabl e, that supports mu ltimediacard system specification version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz, and is compliant with the sd memory card specification version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdio/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is fully compliant with the ce-ata digital protocol rev1.1. 2.2.27 ethernet mac interface with dedicated dma and ieee 1588 support peripheral available only on the STM32F407XX devices. the STM32F407XX devices provid e an ieee-802.3-2002-complia nt media access controller (mac) for ethernet lan communications through an industry-standard medium- independent interface (mii) or a reduced medium-independent interface (rmii). the STM32F407XX requires an external physical interface device (phy) to connect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connected to the STM32F407XX mii port using 17 signals for mii or 9 signals for rmii, and can be clocked using the 25 mhz (mii) from the STM32F407XX. stm32f405xx, STM32F407XX description doc id 022152 rev 1 33/154 the STM32F407XX includes the following features: supports 10 and 100 mbit/s rates dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors (see the stm32f46x reference manual for details) tagged mac frame support (vlan support) half-duplex (csma/cd) and full-duplex operation mac control sublayer (control frames) support 32-bit crc generation and removal several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes. supports hardware ptp (pre cision time protocol) in accordance with ieee 1588 2008 (ptp v2) with the time stamp comparator connected to the tim2 input triggers interrupt when system time becomes greater than target time description stm32f405xx, STM32F407XX 34/154 doc id 022152 rev 1 2.2.28 controller ar ea network (bxcan) the two cans are compliant with the 2.0a and b (active) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). 256 bytes of sram are allocated for each can. 2.2.29 universal se rial bus on-the-go full-speed (otg_fs) the stm32f405xx and STM32F407XX embed an usb otg full-speed device/host/otg peripheral with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 sp ecification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillator. the major features are: combined rx and tx fifo size of 320 35 bits with dynamic fifo sizing supports the session request protocol (srp) and host negotiation protocol (hnp) 4 bidirectional endpoints 8 host channels with periodic out support hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected internal fs otg phy support external fs otg phy support through an i 2 c connection 2.2.30 universal se rial bus on-the-go high-speed (otg_hs) the stm32f405xx and STM32F407XX devices embed a usb otg high-speed (up to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transceivers for full-speed operation (12 mb/s) and features a utmi low-pin interface (ulpi) for high-speed operation (480 mb/s). when using the usb otg hs in hs mode, an external ph y device connected to the ulpi is required. the usb otg hs peripheral is compliant with the usb 2.0 sp ecification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll co nnected to the hse oscillator. stm32f405xx, STM32F407XX description doc id 022152 rev 1 35/154 the major features are: combined rx and tx fifo size of 1 kbit 35 with dynamic fifo sizing supports the session request protocol (srp) and host negotiation protocol (hnp) 6 bidirectional endpoints 12 host channels with periodic out support internal fs otg phy support external fs otg phy support through an i 2 c connection external hs or hs otg operation supporting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. internal usb dma hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected 2.2.31 digital came ra interface (dcmi) the camera interface is not available in stm32f405xx devices. STM32F407XX products embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain a data transfer rate up to 54 mbyte/s at 54 mhz. it features: programmable polarity for the input pixel clock and synchronization signals parallel data communication can be 8-, 10-, 12- or 14-bit supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) supports continuous mode or snapshot (a single frame) mode capability to automati cally crop the image 2.2.32 random num ber generator (rng) all stm32f405xx and STM32F407XX products embed an rng that delivers 32-bit random numbers generated by an integrated analog circuit. 2.2.33 general-purpose input/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or withou t pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allowing maximum i/o toggling up to 84 mhz. description stm32f405xx, STM32F407XX 36/154 doc id 022152 rev 1 2.2.34 analog-to-digit al converte rs (adcs) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: simultaneous sample and hold interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. to synchronize a/d conversion and timers, t he adcs could be triggered by any of tim1, tim2, tim3, tim4, tim5, or tim8 timer. 2.2.35 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.8 v and 3.6 v. the temperature sensor is internally connected to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. as the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.36 digital-to-anal og converter (dac) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. this dual digital interface supports the following features: two dac converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channel independent or simultaneous conversions dma capability for each channel external triggers for conversion input voltage reference v ref+ eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams. 2.2.37 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. stm32f405xx, STM32F407XX description doc id 022152 rev 1 37/154 debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 2.2.38 embedded trace macrocell? the arm embedded trace ma crocell provides a greater visib ility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f40x through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates with third party debugger software tools. pinouts and pin description stm32f405xx, STM32F407XX 38/154 doc id 022152 rev 1 3 pinouts and pin description figure 10. stm32f40x lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6 " ! 4 0 # 0 # . 2 3 4 0 # 0 # 0 # 0 # 6 3 3 ! 6 $ $ ! 0 ! 0 ! 0 ! 6 $ $ 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 # 0 # 0 # 0 ! 0 ! 6 $ $ 6 # ! 0 ? 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 " 0 " 0 " 0 " 0 ! 6 3 3 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 " 0 " 6 # ! 0 ? 6 $ $ , 1 & 0 a i b 0 # 0 ( 0 ( 6 3 3 stm32f405xx, STM32F407XX pinouts and pin description doc id 022152 rev 1 39/154 figure 11. stm32f40x lqfp100 pinout 0 % 0 % 0 % 0 % 0 % 6 " ! 4 0 # 0 # 6 3 3 6 $ $ 0 ( . 2 3 4 0 # 0 # 0 # 0 # 6 $ $ 6 3 3 ! 6 2 % & 6 $ $ ! 0 ! 0 ! 0 ! 6 $ $ 6 3 3 6 # ! 0 ? 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 " 0 " 0 " 0 " 0 ! 6 3 3 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ 6 $ $ 0 $ 2 ? / . 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! a i b , 1 & 0 0 # 0 ( pinouts and pin description stm32f405xx, STM32F407XX 40/154 doc id 022152 rev 1 figure 12. stm32f40x lqfp144 pinout 6 $ $ 0 $ 2 ? / . 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ' 6 $ $ 6 3 3 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 $ 0 $ 6 $ $ 6 3 3 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! 0 % 6 $ $ 0 % 6 3 3 0 % 0 % 0 ! 0 % 0 ! 6 " ! 4 0 ! 0 # 0 ! 0 # 0 ! 0 # 0 ! 0 & 0 # 0 & 0 # 0 & 0 # 0 & 0 # 0 & 6 $ $ 0 & 6 3 3 6 3 3 0 ' 6 $ $ 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 ( 0 $ 0 ( 0 $ . 2 3 4 6 $ $ 0 # 6 3 3 0 # 0 $ 0 # 0 $ 0 # 0 $ 6 3 3 ! 0 $ 6 $ $ 0 $ 6 2 % & 0 $ 6 $ $ ! 0 " 0 ! 0 " 0 ! 0 " 0 ! 0 " 0 ! 6 3 3 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 & 0 & 6 $ $ 0 & 0 & 0 & 0 ' 0 ' 0 % 0 % 0 % 6 3 3 6 $ $ 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ , 1 & 0 a i b 6 # ! 0 ? 6 3 3 stm32f405xx, STM32F407XX pinouts and pin description doc id 022152 rev 1 41/154 figure 13. stm32f40x lqfp176 pinout - 3 6 0 $ 2 ? / . 6 $ $ 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ' 6 $ $ 6 3 3 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 $ 0 $ 6 $ $ 6 3 3 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ) 0 ) 0 % 6 $ $ 0 % 6 3 3 0 % 0 % 0 ! 0 % 0 ! 6 " ! 4 0 ! 0 ) 0 ! 0 # 0 ! 0 # 4 0 ! 0 & 0 # 0 & 0 # 0 & 0 # 0 & 0 # 0 & 6 $ $ 0 & 6 3 3 6 3 3 0 ' 6 $ $ 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 ( 0 $ 0 ( 0 $ . 2 3 4 6 $ $ 0 # 6 3 3 0 # 0 $ 0 # 0 $ 0 # 0 $ 6 3 3 ! 0 $ 6 $ $ 0 $ 6 2 % & 0 $ 6 $ $ ! 0 " 0 ! 0 " 0 ! 0 " 0 ! 0 " 0 ! 6 3 3 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 & 0 & 6 3 3 6 $ $ 0 & 0 & 0 & 0 ' 0 ' 0 % 0 % 0 % 6 3 3 6 $ $ 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ , 1 & 0 6 # ! 0 ? 0 ) 0 ! 0 ! 6 $ $ 6 3 3 0 ) 0 ) 0 ) 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ) 0 ) 0 ( 0 ( 0 ( 6 $ $ 6 3 3 0 ( 0 # 0 ) 0 ) 0 ) 6 3 3 6 $ $ 0 ( 0 ( pinouts and pin description stm32f405xx, STM32F407XX 42/154 doc id 022152 rev 1 figure 14. stm32f40x ufbga176 ballout a i b ! 0 % 0 % 0 % 0 % 0 " 0 " 0 ' 0 ' 0 " 0 " 0 $ 0 # 0 ! 0 ! 0 ! " 0 % 0 % 0 % 0 " 0 " 0 " 0 ' 0 ' 0 ' 0 ' 0 $ 0 $ 0 # 0 # 0 ! # 6 " ! 4 0 ) 0 ) 0 ) 0 $ 2 ? / . 6 $ $ 6 $ $ 6 $ $ 6 $ $ 0 ' 0 $ 0 $ 0 ) 0 ) 0 ! $ 0 # 0 ) 0 ) 0 ) " / / 4 6 3 3 6 3 3 6 3 3 0 $ 0 $ 0 $ 0 ( 0 ) 0 ! % 0 # 0 & 0 ) 0 ) 0 ( 0 ( 0 ) 0 ! & 0 # 6 3 3 6 $ $ 0 ( 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 # ! 0 ? 0 # 0 ! ' 0 ( 6 3 3 6 $ $ 0 ( 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 $ $ 0 # 0 # ( 0 ( 0 & 0 & 0 ( 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 $ $ 0 ' 0 # * . 2 3 4 0 & 0 & 0 ( 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 $ $ 6 $ $ 0 ' 0 ' + 0 & 0 & 0 & 6 $ $ 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 0 ( 0 ' 0 ' 0 ' , 0 & 0 & 0 & " 9 0 ! 3 3 ? 2 % ' 0 ( 0 ( 0 $ 0 ' - 6 3 3 ! 0 # 0 # 0 # 0 # 0 " 0 ' 6 3 3 6 3 3 6 # ! 0 ? 0 ( 0 ( 0 ( 0 $ 0 $ . 6 2 % & 0 ! 0 ! 0 ! 0 # 0 & 0 ' 6 $ $ 6 $ $ 6 $ $ 0 % 0 ( 0 $ 0 $ 0 $ 0 6 2 % & 0 ! 0 ! 0 ! 0 # 0 & 0 & 0 % 0 % 0 % 0 % 0 " 0 " 0 $ 0 $ 2 6 $ $ ! 0 ! 0 ! 0 " 0 " 0 & 0 & 0 % 0 % 0 % 0 % 0 " 0 " 0 " 0 " 6 3 3 stm32f405xx, STM32F407XX pinouts and pin description doc id 022152 rev 1 43/154 table 5. stm32f40x pin and ball definitions pins pin name i / o level function (1) after reset alternate functions (2) lqfp64 lqfp100 lqfp144 ufbga176 lqfp176 -11a21 pe2 ft pe2 traceclk/ fsmc_a23 / eth_mii_txd3 -22a12 pe3 ft pe3 traced0/fsmc_a19 -33b13 pe4 ft pe4 traced1/fsmc_a20 / dcmi_d4 -44b24 pe5 ft pe5 traced2 / fsmc_a21 / tim9_ch1 / dcmi_d6 -55b35 pe6 ft pe6 traced3 / fsmc_a22 / tim9_ch2 / dcmi_d7 166c16 v bat v bat -- -d27 pi8 (3) ft pi8 (4) rtc_af2 277d18 pc13 (3) ft pc13 (4) rtc_af1 388e19 pc14 (3) -osc32_in (5) ft pc14 (4) osc32_in 49 9 f110 pc15 (3) -osc32_out (5) ft pc15 (4) osc32_out -- -d311 pi9 ft pi9 can1_rx -- -e312 pi10 ft pi10 eth_mii_rx_er -- -e413 pi11 ft pi11 otg_hs_ulpi_dir -- - f214 v ss v ss -- - f315 v dd v dd - - 10 e2 16 pf0 ft pf0 fsmc_a0 / i2c2_sda - - 11 h3 17 pf1 ft pf1 fsmc_a1 / i2c2_scl - - 12 h2 18 pf2 ft pf2 fsmc_a2 / i2c2_smba - - 13 j2 19 pf3 (5) ft pf3 fsmc_a3/ adc3_in9 - - 14 j3 20 pf4 (5) ft pf4 fsmc_a4/ adc3_in14 - - 15 k3 21 pf5 (5) ft pf5 fsmc_a5/ adc3_in15 -1016g222 v ss v ss -1117g323 v dd v dd - - 18 k2 24 pf6 (5) ft pf6 tim10_ch1 / fsmc_niord/ adc3_in4 - - 19 k1 25 pf7 (5) ft pf7 tim11_ch1/fsmc_nreg/ adc3_in5 - - 20 l3 26 pf8 (5) ft pf8 tim13_ch1 / fsmc_niowr/ adc3_in6 - - 21 l2 27 pf9 (5) ft pf9 tim14_ch1 / fsmc_cd/ adc3_in7 - - 22 l1 28 pf10 (5) ft pf10 fsmc_intr 51223 g1 29 ph0 (5) -osc_in ft ph0 osc_in 61324 h1 30 ph1 (5) -osc_out ft ph1 osc_out 7 14 25 j1 31 nrst nrst 81526 m2 32 pc0 (5) ft pc0 otg_hs_ulpi_stp/ adc123_in10 91627 m3 33 pc1 (5) ft pc1 eth_mdc/ adc123_in11 10 17 28 m4 34 pc2 (5) ft pc2 spi2_miso / otg_hs_ulpi_dir / th_mii_txd2 /i2s2ext_sd/ adc123_in12 11 18 29 m5 35 pc3 (5) ft pc3 spi2_mosi / i2s2_sd / otg_hs_ulpi_nxt / eth_mii_tx_clk /adc123_in13 pinouts and pin description stm32f405xx, STM32F407XX 44/154 doc id 022152 rev 1 -1930g336 v dd v dd 12 20 31 m1 37 v ssa v ssa -- -n1- v ref ? v ref- -2132 p138 v ref+ v ref+ 13 22 33 r1 39 v dda v dda 14 23 34 n3 40 pa0 (6) -wkup (5) ft pa 0 - w k u p usart2_cts/ usart4_tx/ eth_mii_crs / tim2_ch1_etr/ tim5_ch1 / tim8_etr/ adc123_in0/wkup 15 24 35 n2 41 pa1 (5) ft pa 1 usart2_rts / usart4_rx/ eth_rmii_ref_clk / eth_mii_rx_clk / tim5_ch2 / timm2_ch2/ adc123_in1 16 25 36 p2 42 pa2 (5) ft pa 2 usart2_tx/tim5_ch3 / tim9_ch1 / tim2_ch3 / eth_mdio/ adc123_in2 -- - f443 ph2 ft ph2 eth_mii_crs -- -g444 ph3 ft ph3 eth_mii_col -- -h445 ph4 ft ph4 i2c2_scl / otg_hs_ulpi_nxt -- - j446 ph5 ft ph5 i2c2_sda 17 26 37 r2 47 pa3 (5) ft pa 3 usart2_rx/tim5_ch4 / tim9_ch2 / tim2_ch4 / otg_hs_ulpi_d0 / eth_mii_col/ adc123_in3 18 27 38 - 48 v ss_4 v ss_4 l4 - bypass_reg bypass_ reg 19 28 39 k4 49 v dd v dd 20 29 40 n4 50 pa4 (5) ft pa 4 spi1_nss / spi3_nss / usart2_ck / dcmi_hsync / otg_hs_sof/ i2s3_ws/ adc12_in4 /dac1_out 21 30 41 p4 51 pa5 (5) ft pa 5 spi1_sck/ otg_hs_ulpi_ck / / tim2_ch1_etr/ tim8_chin/ adc12_in5/dac2_out 22 31 42 p3 52 pa6 (5) ft pa 6 spi1_miso / tim8_bkin/tim13_ch1 / dcmi_pixclk / tim3_ch1 / tim1_bkin /adc12_in6 23 32 43 r3 53 pa7 (5) ft pa 7 spi1_mosi/ tim8_ch1n / tim14_ch1 tim3_ch2/ eth_mii_rx _dv / tim1_ch1n / rmii_crs_dv/ adc12_in7 24 33 44 n5 54 pc4 (5) ft pc4 eth_rmii_rx_d0 / eth_mii_rx_d0/ adc12_in14 25 34 45 p5 55 pc5 (5) ft pc5 eth_rmii_rx_d1 / eth_mii_rx_d1/ adc12_in15 26 35 46 r5 56 pb0 (5) ft pb0 tim3_ch3 / tim8_ch2n/ otg_hs_ulpi_d1/ eth_mii_rxd2 / tim1_ch2n/ adc12_in8 27 36 47 r4 57 pb1 (5) ft pb1 tim3_ch4 / tim8_ch3n/ otg_hs_ulpi_d2/ eth_mii_rxd3 / otg_hs_intn / tim1_ch3n/ adc12_in9 28 37 48 m6 58 pb2 ft pb2- boot1 - - 49 r6 59 pf11 ft pf11 dcmi_12 --50p660 pf12 ft pf12 fsmc_a6 --51m861 v ss v ss table 5. stm32f40x pin and ball definitions (continued) pins pin name i / o level function (1) after reset alternate functions (2) lqfp64 lqfp100 lqfp144 ufbga176 lqfp176 stm32f405xx, STM32F407XX pinouts and pin description doc id 022152 rev 1 45/154 --52n862 v dd v dd - - 53 n6 63 pf13 ft pf13 fsmc_a7 - - 54 r7 64 pf14 ft pf14 fsmc_a8 - - 55 p7 65 pf15 ft pf15 fsmc_a9 - - 56 n7 66 pg0 ft pg0 fsmc_a10 - - 57 m7 67 pg1 ft pg1 fsmc_a11 - 38 58 r8 68 pe7 ft pe7 fsmc_d4/tim1_etr - 39 59 p8 69 pe8 ft pe8 fsmc_d5/ tim1_ch1n - 40 60 p9 70 pe9 ft pe9 fsmc_d6/tim1_ch1 --61m971 v ss v ss --62n972 v dd v dd - 41 63 r9 73 pe10 ft pe10 fsmc_d7/tim1_ch2n - 42 64 p10 74 pe11 ft pe11 fsmc_d8/tim1_ch2 - 43 65 r10 75 pe12 ft pe12 fsmc_d9/tim1_ch3n - 44 66 n11 76 pe13 ft pe13 fsmc_d10/tim1_ch3 - 45 67 p11 77 pe14 ft pe14 fsmc_d11/tim1_ch4 - 46 68 r11 78 pe15 ft pe15 fsmc_d12/tim1_bkin 29 47 69 r12 79 pb10 ft pb10 spi2_sck / i2s2_ck / i2c2_scl/ usart3_tx / otg_hs_ulpi_d3 / eth_mii_rx_er / otg_hs_scl / tim2_ch3 30 48 70 r13 80 pb11 ft pb11 i2c2_sda/usart3_rx/ otg_hs_ulpi_d4 / eth_rmii_tx_en/ eth_mii_tx_en / otg_hs_sda / tim2_ch4 31 49 71 m10 81 v cap_1 v cap_1 32 50 72 n10 82 v dd v dd - - - m11 83 ph6 ft ph6 i2c2_smba / tim12_ch1 / eth_mii_rxd2 -- -n1284 ph7 ft ph7 i2c3_scl / eth_mii_rxd3 - - - m12 85 ph8 ft ph8 i2c3_sda / dcmi_hsync - - - m13 86 ph9 ft ph9 i2c3_smba / tim12_ch2/ dcmi_d0 - - - l13 87 ph10 ft ph10 tim5_ch1_etr / dcmi_d1 - - - l12 88 ph11 ft ph11 tim5_ch2 / dcmi_d2 - - - k12 89 ph12 ft ph12 tim5_ch3 / dcmi_d3 -- -h1290 v ss v ss -- -j1291 v dd v dd 33 51 73 p12 92 pb12 ft pb12 spi2_nss / i2s2_ws / i2c2_smba/ usart3_ck/ tim1_bkin / can2_rx / otg_hs_ulpi_d5/ eth_rmii_txd0 / eth_mii_txd0/ otg_hs_id 34 52 74 p13 93 pb13 ft pb13 spi2_sck / i2s2_ck / usart3_cts/ tim1_ch1n /can2_tx / otg_hs_ulpi_d6 / eth_rmii_txd1 / eth_mii_txd1/ otg_hs_vbus table 5. stm32f40x pin and ball definitions (continued) pins pin name i / o level function (1) after reset alternate functions (2) lqfp64 lqfp100 lqfp144 ufbga176 lqfp176 pinouts and pin description stm32f405xx, STM32F407XX 46/154 doc id 022152 rev 1 35 53 75 r14 94 pb14 ft pb14 spi2_miso/ tim1_ch2n / tim12_ch1 / otg_hs_dmusart3_rts / tim8_ch2n/i2s2ext_sd 36 54 76 r15 95 pb15 ft pb15 spi2_mosi / i2s2_sd/ tim1_ch3n / tim8_ch3n / tim12_ch2 / otg_hs_dp - 55 77 p15 96 pd8 ft pd8 fsmc_d13 / usart3_tx - 56 78 p14 97 pd9 ft pd9 fsmc_d14 / usart3_rx - 57 79 n15 98 pd10 ft pd10 fsmc_d15 / usart3_ck - 58 80 n14 99 pd11 ft pd11 fsmc_a16/usart3_cts - 59 81 n13 100 pd12 ft pd12 fsmc_a17/tim4_ch1 / usart3_rts - 60 82 m15 101 pd13 ft pd13 fsmc_a18/tim4_ch2 - - 83 - 102 v ss_8 v ss_8 - - 84 j13 103 v dd v dd - 61 85 m14 104 pd14 ft pd14 fsmc_d0/tim4_ch3 - 62 86 l14 105 pd15 ft pd15 fsmc_d1/tim4_ch4 - - 87 l15 106 pg2 ft pg2 fsmc_a12 - - 88 k15 107 pg3 ft pg3 fsmc_a13 - - 89 k14 108 pg4 ft pg4 fsmc_a14 - - 90 k13 109 pg5 ft pg5 fsmc_a15 - - 91 j15 110 pg6 ft pg6 fsmc_int2 - - 92 j14 111 pg7 ft pg7 fsmc_int3 /usart6_ck - - 93 h14 112 pg8 ft pg8 usart6_rts / eth_pps_out - - 94 g12 113 v ss v ss - - 95 h13 114 v dd v dd 37 63 96 h15 115 pc6 ft pc6 i2s2_mck / tim8_ch1/sdio_d6 / usart6_tx / dcmi_d0/tim3_ch1 38 64 97 g15 116 pc7 ft pc7 i2s3_mck / tim8_ch2/sdio_d7 / usart6_rx / dcmi_d1/tim3_ch2 39 65 98 g14 117 pc8 ft pc8 tim8_ch3/sdio_d0 /tim3_ch3/ usart6_ck / dcmi_d2 40 66 99 f14 118 pc9 ft pc9 i2s_ckin/ mco2 / tim8_ch4/sdio_d1 / /i2c3_sda / dcmi_d3 / tim3_ch4 41 67 100 f15 119 pa8 ft pa8 mco1 / usart1_ck/ tim1_ch1/ i2c3_scl/ otg_fs_sof 42 68 101 e15 120 pa9 ft pa9 usart1_tx/ tim1_ch2 / i2c3_smba / dcmi_d0/ otg_fs_vbus 43 69 102 d15 121 pa10 ft pa10 usart1_rx/ tim1_ch3/ otg_fs_id/dcmi_d1 44 70 103 c15 122 pa11 ft pa11 usart1_cts / can1_rx / tim1_ch4 / otg_fs_dm 45 71 104 b15 123 pa12 ft pa12 usart1_rts / can1_tx/ tim1_etr/ otg_fs_dp 46 72 105 a15 124 pa13 ft jtms-swdio jtms-swdio 47 73 106 f13 125 v cap_2 v cap_2 - 74 107 f12 126 v ss v ss table 5. stm32f40x pin and ball definitions (continued) pins pin name i / o level function (1) after reset alternate functions (2) lqfp64 lqfp100 lqfp144 ufbga176 lqfp176 stm32f405xx, STM32F407XX pinouts and pin description doc id 022152 rev 1 47/154 48 75 108 g13 127 v dd v dd - - - e12 128 ph13 ft ph13 tim8_ch1n / can1_tx - - - e13 129 ph14 ft ph14 tim8_ch2n / dcmi_d4 - - - d13 130 ph15 ft ph15 tim8_ch3n / dcmi_d11 - - - e14 131 pi0 ft pi0 tim5_ch4 / spi2_nss / i2s2_ws / dcmi_d13 - - - d14 132 pi1 ft pi1 spi2_sck / i2s2_ck / dcmi_d8 - - - c14 133 pi2 ft pi2 tim8_ch4 /spi2_miso / dcmi_d9 / i2s2ext_sd - - - c13 134 pi3 ft pi3 tim8_etr / spi2_mosi / i2s2_sd / dcmi_d10 - - - d9 135 v ss v ss - - - c9 136 v dd v dd 49 76 109 a14 137 pa14 ft jtck-swclk jtck-swclk 50 77 110 a13 138 pa15 ft jtdi jtdi/ spi3_nss/ i2s3_ws/tim2_ch1_etr / spi1_nss 51 78 111 b14 139 pc10 ft pc10 spi3_sck / i2s3_ck/ uart4_tx/sdio_d2 / dcmi_d8 / usart3_tx 52 79 112 b13 140 pc11 ft pc11 uart4_rx/ spi3_miso / sdio_d3 / dcmi_d4/usart3_rx / i2s3ext_sd 53 80 113 a12 141 pc12 ft pc12 uart5_tx/sdio_ck / dcmi_d9 / spi3_mosi / i2s3_sd / usart3_ck - 81 114 b12 142 pd0 ft pd0 fsmc_d2/can1_rx - 82 115 c12 143 pd1 ft pd1 fsmc_d3 / can1_tx 54 83 116 d12 144 pd2 ft pd2 tim3_etr/uart5_rx sdio_cmd / dcmi_d11 - 84 117 d11 145 pd3 ft pd3 fsmc_clk/usart2_cts - 85 118 d10 146 pd4 ft pd4 fsmc_noe/usart2_rts - 86 119 c11 147 pd5 ft pd5 fsmc_nwe/usart2_tx - - 120 d8 148 v ss v ss - - 121 c8 149 v dd v dd - 87 122 b11 150 pd6 ft pd6 fsmc_nwait/usart2_rx - 88 123 a11 151 pd7 ft pd7 usart2_ck/fsmc_ne1/fsmc_nce2 - - 124 c10 152 pg9 ft pg9 usart6_rx / fsmc_ne2/ fsmc_nce3 - - 125 b10 153 pg10 ft pg10 fsmc_nce4_1/ fsmc_ne3 - - 126 b9 154 pg11 ft pg11 fsmc_nce4_2 / eth_mii_tx_en/ eth _rmii_tx_en - - 127 b8 155 pg12 ft pg12 fsmc_ne4 / usart6_rts - - 128 a8 156 pg13 ft pg13 fsmc_a24 / usart6_cts /eth_mii_txd0/eth_rmii_txd0 - - 129 a7 157 pg14 ft pg14 fsmc_a25 / usart6_tx /eth_mii_txd1/eth_rmii_txd1 - - 130 d7 158 v ss v ss - - 131 c7 159 v dd v dd table 5. stm32f40x pin and ball definitions (continued) pins pin name i / o level function (1) after reset alternate functions (2) lqfp64 lqfp100 lqfp144 ufbga176 lqfp176 pinouts and pin description stm32f405xx, STM32F407XX 48/154 doc id 022152 rev 1 - - 132 b7 160 pg15 ft pg15 usart6_cts / dcmi_d13 55 89 133 a10 161 pb3 ft jtdo/ traceswo jtdo/ traceswo/ spi3_sck / i2s3_ck / tim2_ch2 / spi1_sck 56 90 134 a9 162 pb4 ft njtrst njtrst/ spi3_miso / tim3_ch1 / spi1_miso / i2s3ext_sd 57 91 135 a6 163 pb5 ft pb5 i2c1_smba/ can2_rx / otg_hs_ulpi_d7 / eth_pps_out/tim3_ch2 / spi1_mosi/ spi3_mosi / dcmi_d10 / i2s3_sd 58 92 136 b6 164 pb6 ft pb6 i2c1_scl/ tim4_ch1 / can2_tx /otg_fs_intn / dcmi_d5/usart1_tx 59 93 137 b5 165 pb7 ft pb7 i2c1_sda / fsmc_nl / dcmi_vsync / usart1_rx/ tim4_ch2 60 94 138 d6 166 boot0 boot0 v pp 61 95 139 a5 167 pb8 ft pb8 tim4_ch3/sdio_d4/ tim10_ch1 / dcmi_d6 / otg_fs_scl/ eth_mii_txd3 / i2c1_scl/ can1_rx 62 96 140 b4 168 pb9 ft pb9 spi2_nss/ i2s2_ws / tim4_ch4/ tim11_ch1/ otg_fs_sda/ sdio_d5 / dcmi_d7 / i2c1_sda / can1_tx - 97 141 a4 169 pe0 ft pe0 tim4_etr / fsmc_nbl0 / dcmi_d2 - 98 142 a3 170 pe1 ft pe1 fsmc_nbl1 / dcmi_d3 63 - - d5 - v ss_3 v ss_3 - 99 143 c6 171 pdr_on pdr_on 64 100 144 c5 172 v dd v dd - - - d4 173 pi4 ft pi4 tim8_bkin / dcmi_d5 - - - c4 174 pi5 ft pi5 tim8_ch1 / dcmi_vsync - - - c3 175 pi6 ft pi6 tim8_ch2 / dcmi_d6 - - - c2 176 pi7 ft pi7 tim8_ch3 / dcmi_d7 1. function availability depends on the chosen device. 2. the functions in bold are rem apped through peripheral registers. 3. pc13, pc14, pc15 and pi8 are supplied through the power switch . since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these i/os must not be us ed as a current source (e.g. to drive an led). 4. main function after the first backup dom ain power-up. later on, it depends on the c ontents of the rtc registers even after reset (because these registers are not reset by the main rese t). for details on how to manage these i/os, refer to the rtc register description sections in the stm32f46x reference manual, avail able from the stmicroel ectronics website: www.st.com. 5. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc 14, pc15, ph0 and ph1). 6. if the device is delivered in an ufbga176 and the bypass_reg pi n is set to vdd (regulator off/internal reset on mode), then pa0 is used as an internal reset (active low). table 5. stm32f40x pin and ball definitions (continued) pins pin name i / o level function (1) after reset alternate functions (2) lqfp64 lqfp100 lqfp144 ufbga176 lqfp176 stm32f405xx, STM32F407XX pinouts and pin description doc id 022152 rev 1 49/154 table 6. alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi pa 0 tim2_ch1 tim2_etr tim 5_ch1 tim8_etr usart2_cts uart4_tx eth_mii_crs eventout pa1 tim2_ch2 tim5_ch2 usart2_rts uart4_rx eth_mii _rx_clk eth_rmii _ref_clk eventout pa2 tim2_ch3 tim5_ch3 tim9_c h1 usart2_tx eth_mdio eventout pa3 tim2_ch4 tim5_ch4 tim9_ch2 usart2_rx otg_hs_ulpi_d0 eth _mii_col eventout pa 4 spi1_nss spi3_nss i2s3_ws usart2_ck otg_hs_sof dcmi_hsync eventout pa 5 tim2_ch1 tim2_etr tim8_ch1n spi1_sck otg_hs_ulpi_ck eventout pa6 tim1_bkin tim3_ch1 tim8_bkin spi1_miso tim13_ch1 dcmi_pixck eventout pa7 tim1_ch1n tim3_ch2 tim8_ch1n spi1_mosi tim14_ch1 eth_mii _rx_dv eth_rmii _crs_dv eventout pa8 mco1 tim1_ch1 i2c3_scl usart1_ck otg_fs_sof eventout pa9 tim1_ch2 i2c3_smba usart1_tx dcmi_d0 eventout pa10 tim1_ch3 usart1_rx otg_fs_id dcmi_d1 eventout pa11 tim1_ch4 usart1_cts can1_rx otg_fs_dm eventout pa12 tim1_etr usart1_rts can1_tx otg_fs_dp eventout pa 1 3 j t m s - s w d i o eventout pa14 jtck-swclk eventout pa 1 5 j t d i tim 2_ch1 tim 2_etr spi1_nss spi3_nss/ i2s3s_ws eventout pb0 tim1_ch2n tim3_ch3 tim8_ch2n otg_hs_ulpi_d1 eth _mii_rxd2 eventout pb1 tim1_ch3n tim3_ch4 tim8_ch3n otg_hs_ulpi_d2 eth _mii_rxd3 otg_hs_intn eventout pb2 eventout pb3 jtdo/ traceswo tim2_ch2 spi1_sck spi3_sck i2s3_ck eventout pb4 jtrst tim3_ch1 spi1_miso spi3_miso i2s3ext_sd eventout pb5 tim3_ch2 i2c1_smba spi1_mosi spi3_mosi i2s3_sd can2_rx otg_hs_ulpi_d7 eth _pps_out dcmi_d10 eventout pb6 tim4_ch1 i2c1_scl i2s2_ws usart1_t x can2_tx otg_fs_intn dcmi_d5 eventout pb7 tim4_ch2 i2c1_sda usart1_rx fsmc_nl dcmi_vsync eventout pb8 tim4_ch3 tim10_ch1 i2c1_scl can1_rx otg_fs_scl eth _mii_txd3 sdio_d4 dcmi_d6 eventout pb9 tim4_ch4 tim11_ch1 i2c1_sda spi2_nss i2s2_ws can1_tx otg_fs_sda sdio_d5 dcmi_d7 eventout pb10 tim2_ch3 i2c2_scl spi2_sck i2s2_ck usart3_tx otg_hs_ulpi_d3 eth_ mii_rx_er otg_hs_scl eventout pb11 tim2_ch4 i2c2_sda usart3_rx otg_hs_ulpi_d4 eth _mii_tx_en eth _rmii_tx_en otg_hs_sda eventout pb12 tim1_bkin i2c2_smba spi2_nss i2s2_ws usart3_ck can2_rx otg_hs_ulpi_d5 eth _mii_txd0 eth _rmii_txd0 otg_hs_id eventout pb13 tim1_ch1n spi2_sck i2s2_ck usart3_cts can2_tx otg_hs_ulpi_d6 eth _mii_txd1 eth _rmii_txd1 eventout pb14 tim1_ch2n tim8_ch2n spi2_miso i2s2ext_sd usart3_rts tim12_ch1 otg_hs_dm eventout pinouts and pin description stm32f405xx, STM32F407XX 50/154 doc id 022152 rev 1 pb15 rtc_50hz tim1_ch3n tim8_ch3n spi2_mosi i2s2_sd tim12_ch2 otg_hs_dp eventout pc0 otg_hs_ulpi_stp eventout pc1 eth_mdc eventout pc2 spi2_miso i2s2ext_sd otg_hs_ulpi_dir eth _mii_txd2 eventout pc3 spi2_mosi i2s2_sd otg_hs_ulpi_nxt eth _mii_tx_clk eth _rmii_tx_clk eventout pc4 eth_mii_rxd0 eth_rmii_rxd0 eventout pc5 eth _mii_rxd1 eth _rmii_rxd1 eventout pc6 tim3_ch1 tim8_ch1 i2s2_mck usart6_tx sdio_d6 dcmi_d0 eventout pc7 tim3_ch2 tim8_ch2 i2s3_mck usart6_rx sdio_d7 dcmi_d1 eventout pc8 tim3_ch3 tim8_ch3 usart6_ck sdio_d0 dcmi_d2 eventout pc9 mco2 tim3_ch4 tim8_ch4 i2c3_sda i2s_ckin sdio_d1 dcmi_d3 eventout pc10 spi3_sck/ i2s3s_ck usart3_tx/ uart4_tx sdio_d2 dcmi_d8 eventout pc11 spi3_miso i2s3ext_sd/ usart3_rx uart4_rx sdio_d3 dcmi_d4 eventout pc12 spi3_mosi i2s3_sd usart3_ck uart5_tx sdio_ck dcmi_d9 eventout pc13 pc14 pc15 pd0 can1_rx fsmc_d2 eventout pd1 can1_tx fsmc_d3 eventout pd2 tim3_etr uart5_rx sdio_cmd dcmi_d11 eventout pd3 usart2_cts fsmc_clk eventout pd4 usart2_rts fsmc_noe eventout pd5 usart2_tx fsmc_nwe eventout pd6 usart2_rx fsmc_nwait eventout pd7 usart2_ck fsmc_ne1/ fsmc_nce2 eventout pd8 usart3_tx fsmc_d13 eventout pd9 usart3_rx fsmc_d14 eventout pd10 usart3_ck fsmc_d15 eventout pd11 usart3_cts fsmc_a16 eventout pd12 tim4_ch1 usart3_rts fsmc_a17 eventout pd13 tim4_ch2 fsmc_a18 eventout pd14 tim4_ch3 fsmc_d0 eventout table 6. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi stm32f405xx, STM32F407XX pinouts and pin description doc id 022152 rev 1 51/154 pd15 tim4_ch4 fsmc_d1 eventout pe0 tim4_etr fsmc_nbl0 dcmi_d2 eventout pe1 fsmc_bln1 dcmi_d3 eventout pe2 traceclk eth _mii_txd3 fsmc_a23 eventout pe3 traced0 fsmc_a19 eventout pe4 traced1 fsmc_a20 dcmi_d4 eventout pe5 traced2 tim9_ch1 fsmc_a21 dcmi_d6 eventout pe6 traced3 tim9_ch2 fsmc_a22 dcmi_d7 eventout pe7 tim1_etr fsmc_d4 eventout pe8 tim1_ch1n fsmc_d5 eventout pe9 tim1_ch1 fsmc_d6 eventout pe10 tim1_ch2n fsmc_d7 eventout pe11 tim1_ch2 fsmc_d8 eventout pe12 tim1_ch3n fsmc_d9 eventout pe13 tim1_ch3 fsmc_d10 eventout pe14 tim1_ch4 fsmc_d11 eventout pe15 tim1_bkin fsmc_d12 eventout pf0 i2c2_sda fsmc_a0 eventout pf1 i2c2_scl fsmc_a1 eventout pf2 i2c2_smba fsmc_a2 eventout pf3 fsmc_a3 eventout pf4 fsmc_a4 eventout pf5 fsmc_a5 eventout pf6 tim10_ch1 fsmc_niord eventout pf7 tim11_ch1 fsmc_nreg eventout pf8 tim13_ch1 fsmc_niowr eventout pf9 tim14_ch1 fsmc_cd eventout pf10 fsmc_intr eventout pf11 dcmi_d12 eventout pf12 fsmc_a6 eventout pf13 fsmc_a7 eventout pf14 fsmc_a8 eventout pf15 fsmc_a9 eventout table 6. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi pinouts and pin description stm32f405xx, STM32F407XX 52/154 doc id 022152 rev 1 pg0 fsmc_a10 eventout pg1 fsmc_a11 eventout pg2 fsmc_a12 eventout pg3 fsmc_a13 eventout pg4 fsmc_a14 eventout pg5 fsmc_a15 eventout pg6 fsmc_int2 eventout pg7 usart6_ck fsmc_int3 eventout pg8 usart6_rts eth _pps_out eventout pg9 usart6_rx fsmc_ne2/ fsmc_nce3 eventout pg10 fsmc_nce4_1/ fsmc_ne3 eventout pg11 eth _mii_tx_en eth _rmii_tx_en fsmc_nce4_2 eventout pg12 usart6_rts fsmc_ne4 eventout pg13 uart6_cts eth _mii_txd0 eth _rmii_txd0 fsmc_a24 eventout pg14 usart6_tx eth _mii_txd1 eth _rmii_txd1 fsmc_a25 eventout pg15 usart6_cts dcmi_d13 eventout ph0 ph1 ph2 eth _mii_crs eventout ph3 eth _mii_col eventout ph4 i2c2_scl otg_hs_ulpi_nxt eventout ph5 i2c2_sda eventout ph6 i2c2_smba tim12_ch1 eth _mii_rxd2 eventout ph7 i2c3_scl eth _mii_rxd3 eventout ph8 i2c3_sda dcmi_hsync eventout ph9 i2c3_smba tim12_ch2 dcmi_d0 eventout ph10 tim5_ch1tim5_etr dcmi_d1 eventout ph11 tim5_ch2 dcmi_d2 eventout ph12 tim5_ch3 dcmi_d3 eventout ph13 tim8_ch1n can1_tx eventout ph14 tim8_ch2n dcmi_d4 eventout table 6. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi stm32f405xx, STM32F407XX pinouts and pin description doc id 022152 rev 1 53/154 ph15 tim8_ch3n dcmi_d11 eventout pi0 tim5_ch4 spi2_nss i2s2_ws dcmi_d13 eventout pi1 spi2_sck i2s2_ck dcmi_d8 eventout pi2 tim8_ch4 spi2_miso i2s2ext_sd dcmi_d9 eventout pi3 tim8_etr spi2_mosi i2s2_sd dcmi_d10 eventout pi4 tim8_bkin dcmi_d5 eventout pi5 tim8_ch1 dcmi_vsync eventout pi6 tim8_ch2 dcmi_d6 eventout pi7 tim8_ch3 dcmi_d7 eventout pi8 pi9 can1_rx eventout pi10 eth _mii_rx_er eventout pi11 otg_hs_ulpi_dir eventout table 6. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi memory map stm32f405xx, STM32F407XX 54/154 doc id 022152 rev 1 4 memory map the memory map is shown in figure 15 . figure 15. memory map - b y t e b l o c k # o r t e x - g s i n t e r n a l p e r i p h e r a l s - b y t e b l o c k . o t u s e d - b y t e b l o c k & 3 - # r e g i s t e r s - b y t e b l o c k & 3 - # b a n k b a n k - b y t e b l o c k & 3 - # b a n k b a n k - b y t e b l o c k 0 e r i p h e r a l s - b y t e b l o c k 3 2 ! - x x & & & & & & & x x & & & & & & & x x & & & & & & & x x & & & & & & & x x & & & & & & & x ! x " & & & & & & & x # x $ & & & & & & & x % x & & & & & & & & - b y t e b l o c k # o d e & l a s h x x & & & & & & & x & & & x & & & ! & x & & & # x & & & # x x & & & & & x x & & & & & & x x & & & & & 3 y s t e m m e m o r y 2 e s e r v e d 2 e s e r v e d ! l i a s e d t o & l a s h s y s t e m m e m o r y o r 3 2 ! - d e p e n d i n g o n t h e " / / 4 p i n s 3 2 ! - + " a l i a s e d b y b i t b a n d i n g 2 e s e r v e d x x " & & & x # x & & & & x x & & & & & & & ! 0 " x 2 e s e r v e d x & & x x & & x 2 e s e r v e d x & & x x & & & & x x & & 2 e s e r v e d x x & & x x " & & x x " & & x 2 e s e t c l o c k c o n t r o l l e r 2 # # x & & 2 e s e r v e d x x & & & # 2 # x x & & 2 e s e r v e d x # x & & & & & & & x ! ( " x ! & & & x ! x " & & & & & & & - 3 6 / p t i o n " y t e s 3 9 3 # & ' 2 e s e r v e d x # x & & & & % 8 4 ) x # x & & & x & & ! ( " x 2 e s e r v e d x & & ! ( " x & & & & x x & & & & & & & 2 e s e r v e d x x & & & & ! ( " x # x x " & & 2 e s e r v e d x x & & ! ( " 3 2 ! - + " a l i a s e d b y b i t b a n d i n g 2 e s e r v e d x & & & # x & & & & & & & x & & & ! x & & & & & & 2 e s e r v e d 4 # - d a t a 2 ! - + " d a t a 3 2 ! - x x & & & & 2 e s e r v e d x x & & % & & & & 2 e s e r v e d ! 0 " ! 0 " ! 0 " x x & & & 2 e s e r v e d x x x & & & & ! ( " x stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 55/154 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.8 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 16 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 17 . figure 16. pin loading condition s figure 17. pin input voltage - 3 6 # p & 3 4 - & p i n / 3 # ? / 5 4 ( i : w h e n u s i n g ( 3 % o r , 3 % - 3 6 3 4 - & p i n 6 ) . / 3 # ? / 5 4 ( i : w h e n u s i n g ( 3 % o r , 3 % electrical characteristics stm32f405xx, STM32F407XX 56/154 doc id 022152 rev 1 5.1.6 power supply scheme figure 18. power supply scheme 1. each power supply pair must be decoupled with filtering ceramic c apacitors as shown above. these capacitors must be placed as close as possible to , or below, the appropriate pins on the undersi de of the pcb to ensure the good functionality of the device. 2. to connect bypass_reg and pdr_on pins, refer to section 2.2.17: real-time clock (rtc), backup sram and backup registers . 3. the two 2.2 f ceramic capacitors should not be connected when the voltage regulator is off. 4. the 4.7 f ceramic capacitor must be connected to one of the vddx pin. 5. v dda =v dd and v ssa =v ss . - 3 6 6 $ $ ! n a l o g 2 # s 0 , , 0 o w e r s w i t c h 6 " ! 4 ' 0 ) / s / 5 4 ) . + e r n e l l o g i c # 0 5 d i g i t a l 2 ! - " a c k u p c i r c u i t r y / 3 # + 2 4 # " a c k u p r e g i s t e r s b a c k u p 2 ! - 7 a k e u p l o g i c n & ? & 6 " ! 4 t o 6 6 o l t a g e r e g u l a t o r 6 3 3 6 $ $ ! 6 2 % & 6 2 % & 6 3 3 ! ! $ # , e v e l s h i f t e r ) / , o g i c 6 $ $ n & ? & 6 2 % & n & ? & 6 $ $ & l a s h m e m o r y 6 # ! 0 ? 6 # ! 0 ? ? & " 9 0 ! 3 3 ? 2 % ' 0 $ 2 ? / . 2 e s e t c o n t r o l l e r stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 57/154 5.1.7 current con sumption measurement figure 19. current consumption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 7: voltage characteristics , table 8: current characteristics , and table 9: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 v bat v dd v dda i dd _v bat i dd table 7. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on five-volt tolerant pin (2) 2. v in maximum value must always be respected. refer to table 8 for the values of the maximum allowed injected current. v ss ?0.3 v dd +4 input voltage on any other pin v ss ?0.3 4.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.14: absolute maximum ratings (electrical sensitivity) electrical characteristics stm32f405xx, STM32F407XX 58/154 doc id 022152 rev 1 5.3 operating conditions 5.3.1 general operating conditions table 8. current characteristics (1) 1. tbd stands for ?to be defined?. symbol ratings max. unit i vdd total current into v dd power lines (source) (2) 2. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. tbd ma i vss total current out of v ss ground lines (sink) (2) tbd i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin 25 i inj(pin) (3) 3. negative injection disturbs the analog performance of the device. see note in section 5.3.20: 12-bit adc characteristics . injected current on five-volt tolerant i/o (4) 4. positive injection is not possible on thes e i/os. a negative injection is induced by v in electrical characteristics stm32f405xx, STM32F407XX 60/154 doc id 022152 rev 1 table 11. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency (f flashmax ) number of wait states at maximum cpu frequency (1) i/o operation fsmc controller operation possible flash memory operations v dd =1.8 to 2.1 v (2) conversion time up to 1.2 msps 16 mhz with no flash memory wait state tbd ? degraded speed performance ? no i/o compensation up to 30 mhz 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1.2 msps 18 mhz with no flash memory wait state 7 (3) ? degraded speed performance ? no i/o compensation up to 30 mhz 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz with no flash memory wait state 6 (3) ? degraded speed performance ? i/o compensation works up to 48 mhz 16-bit erase and program operations v dd = 2.7 to 3.6 v (4) conversion time up to 2.4 msps 30 mhz with no flash memory wait state 5 (3) ? full-speed operation ? i/o compensation works ?up to 60 mhz when v dd = 3.0 to 3.6 v ?up to 48 mhz when v dd = 2.7 to 3.0 v 32-bit erase and program operations 1. the number of wait states can be reduced by reducing the cpu frequency. 2. if pdr_on is set to v ss , this value can be lowered to 1.7 v when the devi ce operates in a reduced temperature range (0 to 70 c). 3. thanks to the art accelerator and the 128-bit flash memory , the number of wait states given here does not impact the execution speed from flash memory since the art accelerator al lows to achieve a performance equivalent to 0 wait state program execution. 4. the voltage range for otg usb fs can drop down to 2.7 v. however it is degraded between 2.7 and 3 v. stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 61/154 5.3.2 vcap1/vcap2 external capacitor stabilization for the main regulato r is achieved by connecting an external capacitor c ext to the vcap1/vcap2 pins. c ext is specified in ta bl e 1 0 and ta b l e 1 2 . figure 20. external capacitor c ext 1. legend: esr is the equivalent series resistance. 5.3.3 operating conditions at power- up / power-down (regulator on) subject to general operating conditions for t a . table 13. operating conditions at power-up / power-down (regulator on) 5.3.4 operating conditions at power- up / power-down (regulator off) subject to general operating conditions for t a . table 12. vcap1/vcap2 operating conditions symbol parameter conditions cext capacitance of external capacitor must be 2.2 f esr esr of external capacitor must be lower than 2 m s 19044v1 e s r r le a k c symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 table 14. operating conditions at power-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below 1.08 v. symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20 electrical characteristics stm32f405xx, STM32F407XX 62/154 doc id 022152 rev 1 5.3.5 embedded reset and power control block characteristics the parameters given in ta bl e 1 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . table 15. embedded reset and power control block characteristics (1) symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 v pls[2:0]=001 (rising edge) 2.23 2.30 2.37 v pls[2:0]=001 (falling edge) 2.13 2.19 2.25 v pls[2:0]=010 (rising edge) 2.39 2.45 2.51 v pls[2:0]=010 (falling edge) 2.29 2.35 2.39 v pls[2:0]=011 (rising edge) 2.54 2.60 2.65 v pls[2:0]=011 (falling edge) 2.44 2.51 2.56 v pls[2:0]=100 (rising edge) 2.70 2.76 2.82 v pls[2:0]=100 (falling edge) 2.59 2.66 2.71 v pls[2:0]=101 (rising edge) 2.86 2.93 2.99 v pls[2:0]=101 (falling edge) 2.65 2.84 3.02 v pls[2:0]=110 (rising edge) 2.96 3.03 3.10 v pls[2:0]=110 (falling edge) 2.85 2.93 2.99 v pls[2:0]=111 (rising edge) 3.07 3.14 3.21 v pls[2:0]=111 (falling edge) 2.95 3.03 3.09 v v pvdhyst (3) pvd hysteresis - 100 - mv v por/pdr power-on/power-down reset threshold falling edge tbd (2) 1.70 tbd v rising edge tbd 1.74 tbd v v pdrhyst (3) pdr hysteresis - 40 - mv stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 63/154 5.3.6 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 19: current consumption measurement scheme . all run mode current consumption measurements given in this section are performed using a coremark-compliant code. typical and maximum current consumption the mcu is placed under the following conditions: at startup, all i/o pins are configured as analog inputs by firmware. all peripherals are disabled except if it is explicitly mentioned. the flash memory access time is adjusted to f hclk frequency (0 wait state from 0 to 30 mhz, 1 wait state from 30 to 60 mhz, 2 wait states from 60 to 90 mhz, 3 wait states v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 v rising edge 2.53 2.59 2.63 v v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 v rising edge 2.85 2.92 2.97 v borhyst (3) bor hysteresis - 100 - mv t rsttempo (3)(4) reset temporization 0.5 1.5 3.0 ms i rush (3) inrush current on voltage regulator power-on (por or wakeup from standby) - 160 200 ma e rush (3) inrush energy on voltage regulator power-on (por or wakeup from standby) v dd = 1.8 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c 1. tbd stands for ?to be defined?. 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 3. guaranteed by design, not tested in production. 4. the reset temporization is measured from the power-on (p or reset or wakeup from v bat ) to the instant when first instruction is read by the user application code. table 15. embedded reset and power control block characteristics (1) (continued) symbol parameter conditions min typ max unit electrical characteristics stm32f405xx, STM32F407XX 64/154 doc id 022152 rev 1 from 90 to 120 mhz, 4 wait states from 120 to 150 mhz, and 5 wait states from 150 to 168 mhz,). when the peripherals are enabled hclk is the system clock, f pclk1 = f hclk /4, and f pclk2 = f hclk /2, except is explicitly mentioned. the maximum values are obtained for v dd = 3.6 v and maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. table 16. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) (1) symbol parameter conditions f hclk typ max (2) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (3) , all peripherals enabled (4) 168 mhz 93.1 tbd tbd ma 144 mhz 76.2 tbd tbd 120 mhz 66.5 tbd tbd 90 mhz 53 tbd tbd 60 mhz 36.7 tbd tbd 30 mhz 20.1 tbd tbd 25 mhz 15.5 tbd tbd 16 mhz (5) 11 tbd tbd 8 mhz 6.4 tbd tbd 4 mhz 4 tbd tbd 2 mhz 2.8 tbd tbd external clock (4) , all peripherals disabled 168 mhz 46.4 tbd tbd 144 mhz 40.3 tbd tbd 120 mhz 36.6 tbd tbd 90 mhz 30 tbd tbd 60 mhz 21.5 tbd tbd 30 mhz 12.2 tbd tbd 25 mhz 9.7 tbd tbd 16 mhz (5) 7.1 tbd tbd 8 mhz 4.4 tbd tbd 4 mhz 3 tbd tbd 2 mhz 2.3 tbd tbd 1. tbd stands for ?to be defined?. 2. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 3. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 4. when the adc is on (adon bit set in the adc_cr2 register ), add an additional power consumption of 1.6 ma per adc for the analog part. 5. in this case hclk = system clock/2. stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 65/154 table 17. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram (1)(2) symbol parameter conditions f hclk typ max (3) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (4) , all peripherals enabled (5) 168 mhz 86.8 tbd tbd ma 144 mhz 67 tbd tbd 120 mhz 56.2 tbd tbd 90 mhz 43.5 tbd tbd 60 mhz 29.7 tbd tbd 30 mhz 16.3 tbd tbd 25 mhz 12.4 tbd tbd 16 mhz (6) 8.7 tbd tbd 8 mhz 5.1 tbd tbd 4 mhz 3.3 tbd tbd 2 mhz 2.4 tbd tbd external clock (4) , all peripherals disabled 168 mhz 39.8 tbd tbd 144 mhz 30.8 tbd tbd 120 mhz 26 tbd tbd 90 mhz 20.4 tbd tbd 60 mhz 14.3 tbd tbd 30 mhz 8.2 tbd tbd 25 mhz 6.4 tbd tbd 16 mhz (6) 4.75 tbd tbd 8 mhz 3 tbd tbd 4 mhz 2.3 tbd tbd 2 mhz 2 tbd tbd 1. code and data processing running from sram1 using boot pins. 2. tbd stands for ?to be defined?. 3. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 4. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 5. when the adc is on (adon bit set in t he adc_cr2 register), add an additional po wer consumption of 1.6 ma per adc for the analog part. 6. in this case hclk = system clock/2. electrical characteristics stm32f405xx, STM32F407XX 66/154 doc id 022152 rev 1 table 18. typical and maximum current consumption in sleep mode (1) symbol parameter conditions f hclk typ max (2) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (3) , all peripherals enabled (4) 168 mhz tbd tbd tbd ma 144 mhz tbd tbd tbd 120 mhz 38 tbd tbd 90 mhz 30 tbd tbd 60 mhz 20 tbd tbd 30 mhz 11 tbd tbd 25 mhz 8 tbd tbd 16 mhz 6 tbd tbd 8 mhz 3.6 tbd tbd 4 mhz 2.4 tbd tbd 2 mhz 1.9 tbd tbd external clock (3) , all peripherals disabled 168 mhz tbd tbd tbd 144 mhz tbd tbd tbd 120 mhz 8 tbd tbd 90 mhz 7 tbd tbd 60 mhz 5 tbd tbd 30 mhz 3.5 tbd tbd 25 mhz 2.5 tbd tbd 16 mhz 2.1 tbd tbd 8 mhz 1.7 tbd tbd 4 mhz 1.5 tbd tbd 2 mhz 1.4 tbd tbd 1. tbd stands for ?to be defined?. 2. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 3. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 4. add an additional power consumption of 0. 8 ma per adc for the analog part. in applic ations, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 67/154 table 19. typical and maximum current consumptions in stop mode (1)(2) symbol parameter conditions typ max unit t a = 25 c t a = 85 c t a = 105 c i dd_stop supply current in stop mode with main regulator in run mode flash in stop mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 1.00 tbd tbd ma flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.98 tbd tbd supply current in stop mode with main regulator in low power mode flash in stop mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.66 tbd tbd flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.63 tbd tbd 1. all typical and maximum values will be further reduced by up to 50% as par t of st continuous improvement of test procedures. new versions of the datasheet will be released to reflect these changes. 2. tbd stands for ?to be defined?. table 20. typical and maximum current consumptions in standby mode (1) symbol parameter conditions typ max unit t a = 25 c t a = 85 c t a = 105 c v dd = 1.8 v v dd = 2.4 v v dd = 3.3 v v dd = 3.6 v i dd_stby supply current in standby mode backup sram on, rtc on tbd tbd tbd tbd (2) tbds (2) a backup sram off, rtc on tbd tbd tbd tbds (2) tbds (2) backup sram on, rtc off tbd tbd tbd tbds (2) tbds (2) backup sram off, rtc off tbd tbd tbd tbds (2) tbds (2) 1. tbd stands for ?to be defined?. 2. based on characterization, not tested in production. electrical characteristics stm32f405xx, STM32F407XX 68/154 doc id 022152 rev 1 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in table 43: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog pins. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 23: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: table 21. typical and maximum current consumptions in v bat mode (1) symbol parameter conditions typ max unit t a = 25 c t a = 85 c t a = 105 c v dd = 1.8 v v dd = 2.4 v v dd = 3.3 v v dd = 3.6 v i dd_vbat backup domain supply current backup sram on, rtc on tbd tbd tbd tbd (2) tbd (2) a backup sram off, low-speed oscillator and rtc on tbd tbd tbd tbd (2) tbd (2) backup sram on, rtc off tbd tbd tbd tbd (2) tbd (2) backup sram off, rtc off tbd tbd tbd tbd (2) tbd (2) 1. tbd stands for ?to be defined?. 2. based on characterization, not tested in production. i sw v dd f sw c = stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 69/154 where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the /o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. table 22. switching output i/o current consumption (1) symbol parameter conditions i/o toggling frequency (f sw ) typ unit i ddio supply current v dd = 3.3 v c ext = 20 pf tbd tbd ma tbd tbd tbd tbd tbd tbd tbd tbd v dd = 3.3 v c ext = 50 pf tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd v dd = 2.4v c ext = 20pf tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd v dd = 2.4v c ext = 50pf tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 1. tbd stands for ?to be defined?. electrical characteristics stm32f405xx, STM32F407XX 70/154 doc id 022152 rev 1 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 2 3 . the mcu is placed under the following conditions: at startup, all i/o pins are configured as analog pins by firmware. all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with one peripheral clocked on (with only the clock applied) the code is running from flash memory and the flash memory access time is equal to 3 wait states at 120 mhz, 4 wait states at 144 mhz, and 5 wait states at 168 mhz. prefetch and cache on when the peripherals are enabled, hclk = 120/144/168 mhz, f pclk1 = f hclk /4, and f pclk2 =f hclk /2 the typical values are obtained for v dd = 3.3 v and t a = 25 c, unless otherwise specified. table 23. peripheral current consumption (1) peripheral (2) typical consumption at 25 c unit ahb1 gpio a tbd ma gpio b tbd gpio c tbd gpio d tbd gpio e tbd gpio f tbd gpio g tbd gpio h tbd gpio i tbd otg_hs + ulpi tbd crc tbd bkpsram tbd dma1 tbd dma2 tbd eth_mac + eth_mac_tx eth_mac_rx eth_mac_ptp tbd ahb2 otg_fs tbd dcmi tbd ahb3 fsmc tbd stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 71/154 apb1 tim2 tbd ma tim3 tbd tim4 tbd tim5 tbd tim6 tbd tim7 tbd tim12 tbd tim13 tbd tim14 tbd usart2 tbd usart3 tbd uart4 tbd uart5 tbd i2c1 tbd i2c2 tbd i2c3 tbd spi2 tbd spi3 tbd can1 tbd can2 tbd dac channel 1 (3) tbd dac channel 1 (4) tbd pwr tbd wwdg tbd table 23. peripheral current consumption (1) (continued) peripheral (2) typical consumption at 25 c unit electrical characteristics stm32f405xx, STM32F407XX 72/154 doc id 022152 rev 1 5.3.7 wakeup time from low-power mode the wakeup times given in ta bl e 2 4 is measured on a wakeup phase with a 16 mhz hsi rc oscillator. the clock source used to wake up the device depe nds from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 0 . apb2 sdio tbd ma tim1 tbd tim8 tbd tim9 tbd tim10 tbd tim11 tbd adc1 (5) tbd adc2 (5) tbd adc3 (5) tbd spi1 tbd usart1 tbd usart6 tbd 1. tbd stands for ?to be defined?. 2. external clock is 25 mhz (hse oscillat or with 25 mhz crystal) and pll is on. 3. en1 bit is set in dac_cr register. 4. en2 bit is set in dac_cr register. 5. f adc = f pclk2 /2, adon bit set in adc_cr2 register. table 23. peripheral current consumption (1) (continued) peripheral (2) typical consumption at 25 c unit table 24. low-power mode wakeup timings symbol parameter min (1) typ (1) max (1) unit t wusleep (2) wakeup from sleep mode - 1 - s t wustop (2) wakeup from stop mode (regulator in run mode) - 13 - s wakeup from stop mode (regulator in low power mode) - 17 40 wakeup from stop mode (regulator in low power mode and flash memory in deep power down mode) -110- t wustdby (2)(3) wakeup from standby mode 260 375 480 s 1. based on characterization, not tested in production. 2. the wakeup times are measured from the wakeup event to the point in which the application c ode reads the first instruction. 3. t wustdby minimum and maximum values are given at 105 c and ?45 c, respectively. stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 73/154 5.3.8 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 2 5 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 1 0 . low-speed external user clock generated from an external source the characteristics given in ta b l e 2 6 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 1 0 . table 25. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) 1826mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design, not tested in production. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --20 c in(hse) osc_in input capacitance (1) -5-pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a table 26. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) -tbd (2) -pf ducy (lse) duty cycle 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a 1. guaranteed by design, not tested in production. 2. tbd stands for ?to be defined?. electrical characteristics stm32f405xx, STM32F407XX 74/154 doc id 022152 rev 1 figure 21. high-speed external clock source ac timing diagram figure 22. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 7 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). a i1752 8 o s c_in extern a l s tm 3 2f clock s o u rce v h s eh t f(h s e) t w(h s e) i l 90 % 10 % t h s e t t r(h s e) t w(h s e) f h s e_ext v h s el a i17529 o s c 3 2_in extern a l s tm 3 2f clock s o u rce v l s eh t f(l s e) t w(l s e) i l 90 % 10 % t l s e t t r(l s e) t w(l s e) f l s e_ext v l s el stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 75/154 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 23 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available fr om the st website www.st.com. figure 23. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 8 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 27. hse 4-26 mhz oscillator characteristics (1) (2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization , not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 - 26 mhz r f feedback resistor - 200 - k c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 -15-pf i 2 hse driving current v dd = 3.3 v, v in =v ss with 30 pf load --1ma g m oscillator transconductance startup 5 - - ma/v t su(hse (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms a i175 3 0 o s c_ou t o s c_in f h s e c l1 r f s tm 3 2f 8 mh z re s on a tor re s on a tor with integr a ted c a p a citor s bi as controlled g a in r ext (1) c l2 electrical characteristics stm32f405xx, STM32F407XX 76/154 doc id 022152 rev 1 note: for c l1 and c l2 it is recommended to use high-quality external ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator (see figure 24 ). c l1 and c l2, are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. figure 24. typical application with a 32.768 khz crystal table 28. lse oscillator characteristics (f lse = 32.768 khz) (1)(2) 1. based on characterization , not tested in production. 2. tbd stands for ?to be defined?. symbol parameter conditions min typ max unit r f feedback resistor - tbd - m c (3) 3. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (4) 4. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value for example msiv-tin32.768khz. refer to crystal manufacturer for more details r s = 30 k --tbdpf i 2 lse driving current v dd = 3.3 v, v in = v ss --tbda g m oscillator transconductance tbd - - a/v t su(lse) (5) 5. t su(lse) is the startup time measured from the mom ent it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard cr ystal resonator and it can vary significantly with t he crystal manufacturer startup time v dd is stabilized - tbd - s a i175 3 1 o s c 3 2_ou t o s c 3 2_in f l s e c l1 r f s tm 3 2f 3 2.76 8 kh z re s on a tor re s on a tor with integr a ted c a p a citor s bi as controlled g a in c l2 stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 77/154 5.3.9 internal clock source characteristics the parameters given in ta bl e 2 9 and ta b l e 3 0 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 0 . high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator table 29. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 16 - mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibrat ion? available from the st website www.st.com. --1% factory- calibrated t a = ?40 to 105 c ?8 - 4.5 % t a = ?10 to 85 c ?4 - 4 % t a = 25 c ?1 - 1 % t su(hsi) (3) 3. guaranteed by design, not tested in production. hsi oscillator startup time -2.24 s i dd(hsi) hsi oscillator power consumption -6080a table 30. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on characterization , not tested in production. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a electrical characteristics stm32f405xx, STM32F407XX 78/154 doc id 022152 rev 1 figure 25. acc lsi versus temperature 5.3.10 pll characteristics the parameters given in ta bl e 3 1 and ta b l e 3 2 are derived from tests performed under temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . - 3 6 . o r m a l i z e d d e v i a t i o n 4 e m p e r a t u r e ? # m a x a v g m i n table 31. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) 0.95 (2) 12.0 (3) mhz f pll_out pll multiplier output clock 24 - 168 mhz f pll48_out 48 mhz pll multiplier output clock -48 -mhz f vco_out pll vco output 192 - 432 mhz t lock pll lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 79/154 jitter (4) cycle-to-cycle jitter system clock 120 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - main clock output (mco) for rmii ethernet cycle to cycle at 50 mhz on 1000 samples -32 - main clock output (mco) for mii ethernet cycle to cycle at 25 mhz on 1000 samples -40 - bit time can jitter cycle to cycle at 1 mhz on 1000 samples -330 - main clock output (mco) for rmmi ethernet long term jitter, pll input=6.25mhz -1.6 -ns i dd(pll) (5) pll power consumption on vdd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (5) pll power consumption on vdda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division factor m to obtain the specified pll input clock va lues. the m factor is shared between pll and plli2s. 2. guaranteed by design, not tested in production. 3. maximum input pll frequency is recommended for a pplications sensitive of long term jitter. 4. the use of 2 plls in parallel could degraded the jitter up to +30%. 5. based on characterization, not tested in production. table 31. main pll characteristics (continued) symbol parameter conditions min typ max unit table 32. plli2s (audio pll) characteristics (1) symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (2) 0.95 (3) 12.0 (4) mhz f plli2s_out plli2s multiplier output clock - - 216 mhz f vco_out plli2s vco output 192 - 432 mhz t lock plli2s lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 electrical characteristics stm32f405xx, STM32F407XX 80/154 doc id 022152 rev 1 jitter (5) master i2s clock jitter cycle to cycle at 12,343 mhz on 48khz period, n=432, p=4, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12,343 mhz n=432, p=4, r=5 on 256 samples tbd - tbd ps ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples - 400 - ps i dd(plli2s) (6) plli2s power consumption on v dd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (6) plli2s power consumption on v dda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. tbd stands for ?to be defined?. 2. take care of using the appropriate division factor m to have the specified pll input clock values. 3. guaranteed by design, not tested in production. 4. maximum input pll frequency is recommended for a pplications sensitive of long term jitter. 5. value given with main pll running. 6. based on characterization, not tested in production. table 32. plli2s (audio pll) characteristics (1) (continued) symbol parameter conditions min typ max unit stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 81/154 5.3.11 pll spread spectrum clock generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 39: emi characteristics ). it is available only on the main pll. equation 1 the frequency mo dulation period (modeper) is gi ven by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation depth (modeper) is given by equation 1: equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and f vco_out = 240 (in mhz): an amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: the error in modulation depth is consequently: 2.0 - 1.99954 = 0.00046%. table 33. sscg parameters constraint symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - 2 15 ? 1- 1. guaranteed by design, not tested in production. modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 25 == incstep round 2 15 1 ? () md f vco_out () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2 240 () 100 5 25 () ? [] 1258md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () f vco_out () ? = md quantized % 25 1258 100 5 () 2 15 1 ? () 240 () ? 1.99954%(peak) == electrical characteristics stm32f405xx, STM32F407XX 82/154 doc id 022152 rev 1 figure 26 and figure 27 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 26. pll output clock waveforms in center spread mode figure 27. pll output clock waveforms in down spread mode 5.3.12 memory characteristics flash memory the characteristics are given at t a = ? 40 to 105 c unless otherwise specified. & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e t m o d e m d a i m d & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e t m o d e m d a i table 34. flash memory characteristics (1) 1. tbd stands for ?to be defined?. symbol parameter conditions min max unit i dd supply current read mode f hclk = 168 mhz with 4 wait states, v dd = 3.3 v -tbdma write / erase modes f hclk = 168 mhz, v dd = 3.3 v -tbdma stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 83/154 table 35. flash memory programming (1) 1. tbd stands for ?to be defined?. symbol parameter conditions min (2) typ max (2) 2. based on characterization , not tested in production. unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (3) 3. the maximum programming time is m easured after 100k erase operations. s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.32.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -16tbd s program/erase parallelism (psize) = x 16 -11tbd program/erase parallelism (psize) = x 32 -8tbd v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.8 - 3.6 v electrical characteristics stm32f405xx, STM32F407XX 84/154 doc id 022152 rev 1 table 37. flash memory endurance and data retention 5.3.13 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. table 36. flash memory programming with v pp (1) 1. tbd stands for ?to be defined?. symbol parameter conditions min (2) typ max (2) 2. guaranteed by design, not tested in production. unit t prog double word programming t a = 0 to +40 c - 16 100 (3) 3. the maximum programming time is m easured after 100k erase operations. s t erase16kb sector (16 kb) erase time - tbd - t erase64kb sector (64 kb) erase time - tbd - t erase128kb sector (128 kb) erase time - tbd - t me mass erase time - 6.8 - v prog programming voltage 2.7 - 3.6 v v pp v pp voltage range 7 - 9 v i pp minimum current sunk on the v pp pin 10 - - ma t vpp (4) 4. v pp should only be connected du ring programming/erasing. cumulative time during which v pp is applied - - 1 hour symbol parameter conditions value unit min (1) 1. based on characterization , not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 85/154 a device reset allows normal operations to be resumed. the test results are given in ta b l e 3 8 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 38. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 84 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 84 mhz, conforms to iec 61000-4-2 4a electrical characteristics stm32f405xx, STM32F407XX 86/154 doc id 022152 rev 1 electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc ? code, is running. this emission te st is compliant wi th sae iec61967-2 standard which specifies the test board and the pin loading. 5.3.14 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 39. emi characteristics (1) symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 8/120 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running with art enabled 0.1 to 30 mhz tbd dbv 30 to 130 mhz tbd 130 mhz to 1ghz tbd sae emi level tbd - v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running with art enabled, pll spread spectrum enabled 0.1 to 30 mhz tbd dbv 30 to 130 mhz tbd 130 mhz to 1ghz tbd sae emi level tbd - 1. tbd stands for ?to be defined?. table 40. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to jesd22-a114 2 2000 (2) v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to jesd22-c101 ii 500 1. based on characterization results, not tested in production. 2. on v bat pin, v esd(hbm) is limited to 1000 v. stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 87/154 static latchup two complementary static tests are required on six parts to assess the latchup performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latchup standard. 5.3.15 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibilit y tests are performed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). the test results are given in ta b l e 4 2 . table 41. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 42. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on all ft pins ?5 +0 ma injected current on any other pin ?5 +5 electrical characteristics stm32f405xx, STM32F407XX 88/154 doc id 022152 rev 1 5.3.16 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 4 3 are derived from tests performed under the conditions summarized in ta b l e 1 0 . all i/os are cmos and ttl compliant. table 43. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage ttl ports 2.7 v v dd 3.6 v v ss ?0.3 - 0.8 v v ih (1) tt (2) i/o input high level voltage 2.0 - v dd +0.3 ft (3) i/o input high level voltage 2.0 - 5.5 v il input low level voltage cmos ports 1.8 v v dd 3.6 v v ss ?0.3 - 0.3v dd v ih (1) tt i/o input high level voltage 0.7v dd -3.6 (4) ft i/o input high level voltage -5.2 (4) cmos ports 2.0 v v dd 3.6 v -5.5 (4) v hys i/o schmitt trigger voltage hysteresis (5) -200- mv io ft schmitt trigger voltage hysteresis (5) 5% v dd (4) - - i lkg i/o input leakage current (6) v ss v in v dd -- 1 a i/o ft input leakage current (6) v in = 5v - - 3 r pu weak pull-up equivalent resistor (7) all pins except for pa10 and pb12 v in = v ss 30 40 50 k pa10 and pb12 81115 r pd weak pull-down equivalent resistor all pins except for pa10 and pb12 v in = v dd 30 40 50 pa10 and pb12 81115 c io (8) i/o pin capacitance 5 pf 1. if v ih maximum value cannot be respected, the inject ion current must be limited externally to i inj(pin) maximum value. 2. tt = 3.6 v tolerant. 3. ft = 5 v tolerant. 4. with a minimum of 100 mv. 5. hysteresis voltage between schmitt trigger switching leve ls. based on characterization, not tested in production. 6. leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 7. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) . 8. guaranteed by design, not tested in production. stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 89/154 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 . in particular: the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 8 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 8 ). output voltage levels unless otherwise specified, the parameters given in ta bl e 4 4 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 0 . all i/os are cmos and ttl compliant. table 44. output voltage characteristics (1) 1. pc13, pc14, pc15 and pi8 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these i/os must not be used as a current source (e.g. to drive an led). symbol parameter conditions min max unit v ol (2) 2. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 8 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time ttl port i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 8 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 - v ol (2) output low level voltage for an i/o pin when 8 pins are sunk at same time cmos port i io =+ 8ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 - v ol (2)(4) 4. based on characterization data, not tested in production. output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 - v ol (2)(4) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma 2 v < v dd < 2.7 v -0.4 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 - electrical characteristics stm32f405xx, STM32F407XX 90/154 doc id 022152 rev 1 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 28 and ta bl e 4 5 , respectively. unless otherwise specified, the parameters given in ta bl e 4 5 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . table 45. i/o ac characteristics (1)(2) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd > 2.70 v - - 2 mhz c l = 50 pf, v dd > 1.8 v - - 2 c l = 10 pf, v dd > 2.70 v - - tbd c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, v dd = 1.8 v to 3.6 v --tbd ns t r(io)out output low to high level rise time --tbd 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd > 2.70 v - - 25 mhz c l = 50 pf, v dd > 1.8 v - - 12.5 (4) c l = 10 pf, v dd > 2.70 v - - 50 (4) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 50 pf, v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd 10 f max(io)out maximum frequency (3) c l = 40 pf, v dd > 2.70 v - - 50 (4) mhz c l = 40 pf, v dd > 1.8 v - - 25 c l = 10 pf, v dd > 2.70 v - - 100 (4) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, 2.4 < v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 50 pf, 2.4 < v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 91/154 figure 28. i/o ac characteristics definition 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd > 2.70 v - - 100 (4) mhz c l = 30 pf, v dd > 1.8 v - - 50 (4) c l = 10 pf, v dd > 2.70 v - - 200 (4) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 20 pf, 2.4 < v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 20 pf, 2.4 < v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd -t extipw pulse width of external signals detected by the exti controller 10 - - ns 1. the i/o speed is configured using the ospeedry[1:0] bi ts. refer to the stm32f20/21xxx reference manual for a description of the gpiox_speedr gpio port output speed register. 2. tbd stands for ?to be defined?. 3. the maximum frequency is defined in figure 28 . 4. for maximum frequencies above 50 mhz, the compensation cell should be used. table 45. i/o ac characteristics (1)(2) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50pf t t r(io)out electrical characteristics stm32f405xx, STM32F407XX 92/154 doc id 022152 rev 1 5.3.17 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 4 3 ). unless otherwise specified, the parameters given in ta bl e 4 6 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . figure 29. recommended nrst pin protection 2. the reset network protects t he device against par asitic resets. 3. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 46 . otherwise the reset is not taken into account by the device. table 46. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 - 0.8 v v ih(nrst) (1) nrst input high level voltage 2 - v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 30 40 50 k v f(nrst) (1) nrst input filtered pulse - - 100 ns v nf(nrst) (1) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s a i c 3 4 - & x x x 2 0 5 . 2 3 4 6 $ $ & i l t e r ) n t e r n a l 2 e s e t ? & % x t e r n a l r e s e t c i r c u i t stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 93/154 5.3.18 tim time r characteristics the parameters given in ta bl e 4 7 and ta b l e 4 8 are guaranteed by design. refer to section 5.3.16: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 47. characteristics of timx connected to the apb1 domain (1)(2) 1. timx is used as a general term to refer to the tim2, tim3, tim4, tim5, tim6, tim7, and tim12 timers. 2. tbd stands for ?to be defined?. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb1 prescaler distinct from 1, f timxclk = 84 mhz 1- t timxclk 11.9 - ns ahb/apb1 prescaler = 1, f timxclk = 42 mhz 1- t timxclk 23.8 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 84 mhz apb1= 42 mhz 0 f timxclk /2 mhz 042mhz res tim timer resolution - 16/32 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk 0.0119 tbd s 32-bit counter clock period when internal clock is selected 1- t timxclk 0.0119 tbd s t max_count maximum possible count - 65536 65536 t timxclk -tbd s electrical characteristics stm32f405xx, STM32F407XX 94/154 doc id 022152 rev 1 5.3.19 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 4 9 are derived from tests performed under the ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta bl e 1 0 . the stm32f405xx and STM32F407XX i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 4 9 . refer also to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 48. characteristics of timx connected to the apb2 domain (1) 1. timx is used as a general term to refer to the tim1, tim8, tim9, tim10, and tim11 timers. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb2 prescaler distinct from 1, f timxclk = 168 mhz 1- t timxclk 5.95 - ns ahb/apb2 prescaler = 1, f timxclk = 84 mhz 1- t timxclk 11.9 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 168 mhz apb2 = 84 mhz 0 f timxclk /2 mhz 084mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk 0.00595 tbd s t max_count maximum possible count - 65536 65536 t timxclk - tbd (2) 2. tbd stands for ?to be defined?. s stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 95/154 table 49. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1)(2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies, and a multiple of 10 mhz to reach the 400 khz maximum i 2 c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. -0 (4) 4. the device must internally provide a hold time of at least 300ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf electrical characteristics stm32f405xx, STM32F407XX 96/154 doc id 022152 rev 1 figure 30. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 50. scl frequency (f pclk1 = 42 mhz.,v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012c 20 0x02ee a i b 3 4 ! 2 4 3 $ ! k ) # b u s k 6 $ $ 6 $ $ 3 4 - & x x 3 $ ! 3 # , t f 3 $ ! t r 3 $ ! 3 # , t h 3 4 ! t w 3 # , ( t w 3 # , , t s u 3 $ ! t r 3 # , t f 3 # , t h 3 $ ! 3 4 ! 2 4 2 % 0 % ! 4 % $ 3 4 ! 2 4 t s u 3 4 ! t s u 3 4 / 3 4 / 0 t w 3 4 / 3 4 ! stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 97/154 i 2 s - spi interface characteristics unless otherwise specified, the parameters given in ta bl e 5 1 for spi or in ta bl e 5 2 for i 2 s are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 1 0 . refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 51. spi characteristics (1)(2) 1. remapped spi1 characteristics to be determined. 2. tbd stands for ?to be defined?. symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 37.5 mhz slave mode - 37.5 t r(scl) t f(scl) spi clock rise and fall time capacitive load: c = 30 pf - 8 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (3) 3. based on characterization , not tested in production. nss setup time slave mode 4 t pclk - ns t h(nss) (3) nss hold time slave mode 2 t pclk - t w(sclh) (3) t w(scll) (3) sck high and low time master mode, f pclk = 42 mhz, presc = 4 tbd tbd t su(mi) (3) t su(si) (3) data input setup time master mode 5 - slave mode 5 - t h(mi) (3) t h(si) (3) data input hold time master mode 5 - slave mode 4 - t a(so) (3)(4) 4. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 20 mhz 0 3 t pclk t dis(so) (3)(5) 5. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (3)(1) data output valid time slave mode (after enable edge) - 25 t v(mo) (3)(1) data output valid time master mode (after enable edge) - 5 t h(so) (3) data output hold time slave mode (after enable edge) 15 - t h(mo) (3) master mode (after enable edge) 2 - electrical characteristics stm32f405xx, STM32F407XX 98/154 doc id 022152 rev 1 figure 31. spi timing diagram - slave mode and cpha = 0 figure 32. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 99/154 figure 33. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) electrical characteristics stm32f405xx, STM32F407XX 100/154 doc id 022152 rev 1 table 52. i 2 s characteristics (1) 1. tbd stands for ?to be defined?. symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master tbd 37.5 mhz slave 0 37.5 t r(ck) t f(ck) i 2 s clock rise and fall time capacitive load c l = 50 pf - tbd ns t v(ws) (2) 2. based on design simulation and/or characte rization results, not tested in production. ws valid time master tbd - t h(ws) (2) ws hold time master tbd - t su(ws) (2) ws setup time slave tbd - t h(ws) (2) ws hold time slave tbd - t w(ckh) (2) t w(ckl) (2) ck high and low time master f pclk = tbd, presc = tbd tbd - t su(sd_mr) (2) t su(sd_sr) (2) data input setup time master receiver slave receiver tbd tbd - t h(sd_mr) (2)(3) t h(sd_sr) (2)(3) 3. depends on f pclk . for example, if f pclk =8 mhz, then t pclk = 1/f plclk =125 ns. data input hold time master receiver slave receiver tbd tbd - t h(sd_mr) (2) t h(sd_sr) (2) data input hold time master f pclk = tbd slave f pclk = tbd tbd tbd - t v(sd_st) (2)(3) data output valid time slave transmitter (after enable edge) - tbd f pclk = tbd - tbd t h(sd_st) (2) data output hold time slave transmitter (after enable edge) tbd - t v(sd_mt) (2)(3) data output valid time master transmitter (after enable edge) - tbd f pclk = tbd tbd tbd t h(sd_mt) (2) data output hold time master transmitter (after enable edge) tbd - stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 101/154 figure 34. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 35. i 2 s master timing diagram (philips protocol) (1) 1. based on characterization , not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2) electrical characteristics stm32f405xx, STM32F407XX 102/154 doc id 022152 rev 1 usb otg fs characteristics the usb otg interface is usb-if certified (full-spee d). this interface is present in both the usb otg hs and usb otg fs controllers. table 53. usb otg fs startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb otg fs transceiver startup time 1 s table 54. usb otg fs dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg fs operating voltage 3.0 (2) 2. the stm32f405xx and STM32F407XX usb otg fs functi onality is ensured down to 2.7 v but not the full usb otg fs electrical c haracteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. -3.6v v di (3) 3. guaranteed by design, not tested in production. differential input sensitivity i(usb_fs_dp/dm, usb_hs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold 1.3 - 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb otg fs drivers --0.3 v v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12, pb14, pb15 (usb_fs_dp/dm, usb_hs_dp/dm) v in = v dd 17 21 24 k pa9, pb13 (otg_fs_vbus, otg_hs_vbus) 0.65 1.1 2.0 r pu pa12, pb15 (usb_fs_dp, usb_hs_dp) v in = v ss 1.5 1.8 2.1 pa9, pb13 (otg_fs_vbus, otg_hs_vbus) v in = v ss 0.25 0.37 0.55 stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 103/154 figure 36. usb otg fs timings: definiti on of data signal rise and fall time table 55. usb otg fs electrical characteristics (1) 1. guaranteed by design, not tested in production. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapt er 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v table 56. usb fs clock timing parameters (1)(2) 1. guaranteed by design, not tested in production. 2. tbd stands for ?to be defined?. parameter symbol min nominal max unit f hclk value to guarantee proper operation of usb fs interface -tbd mhz ahb frequency for correct usb fs operation - 14.2 mhz frequency (first transition) 8-bit 10% f start_8bit tbd tbd tbd mhz frequency (steady state) 500 ppm f steady tbd tbd tbd mhz duty cycle (first transition) 8-bit 10% d start_8bit tbd tbd tbd % duty cycle (steady state) 500 ppm d steady tbd tbd tbd % time to reach the stea dy state frequency and duty cycle after the first transition t steady --tbdms clock startup time after the de-assertion of suspendm peripheral t start_dev --tbd ms host t start_host --- phy preparation time after the first transition of the input clock t prep ---s ai14137 t f differen tial data lines v ss v cr s t r crossover points electrical characteristics stm32f405xx, STM32F407XX 104/154 doc id 022152 rev 1 usb hs characteristics ta bl e 5 7 shows the usb hs operating voltage. figure 37. ulpi timing diagram table 57. usb hs dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd ethernet operating voltage 2.7 3.6 v table 58. usb hs clock timing parameters (1) 1. guaranteed by design, not tested in production. parameter symbol min nominal max unit f hclk value to guarantee proper operation of usb hs interface tbd mhz frequency (first transition) 8-bit 10% f start_8bit 54 60 66 mhz frequency (steady state) 500 ppm f steady 59.97 60 60.03 mhz duty cycle (first transition) 8-bit 10% d start_8bit 40 50 60 % duty cycle (steady state) 500 ppm d steady 49.975 50 50.025 % time to reach the stea dy state frequency and duty cycle after the first transition t steady --1.4ms clock startup time after the de-assertion of suspendm peripheral t start_dev --5.6 ms host t start_host --- phy preparation time after the first transition of the input clock t prep ---s # l o c k # o n t r o l ) n s t p d a t a ) n b i t # o n t r o l o u t d i r n x t d a t a o u t b i t d a t a o u t b i t t $ $ $ t $ $ $ t $ $ t $ # t $ # t ( $ t 3 $ t ( # t 3 # a i b stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 105/154 ethernet characteristics ta bl e 6 0 shows the ethernet operating voltage. ta bl e 6 1 gives the list of ethernet mac signals for the smi (station management interface) and figure 38 shows the corresponding timing diagram. figure 38. ethernet smi timing diagram table 59. ulpi timing parameter symbol value (1) 1. v dd = 2.7 v to 3.6 v and t a = ?40 to 85 c. unit min. max. output clock setup time (control in) t sc , t sd -6.0ns hold time (control in) t hc , t hd 0.0 - ns output delay (control out) t dc , t dd -9.0ns input clock (optional) setup time (control in) t sc , t sd -3.0ns hold time (control in) t hc , t hd 1.5 - ns output delay (control out) t dc , t dd -6.0ns table 60. ethernet dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd ethernet operating voltage 2.7 3.6 v table 61. dynamics characteristics: ethernet mac signals for smi (1) 1. tbd stands for ?to be defined?. symbol rating min typ max unit t mdc mdc cycle time (1.71 mhz, ahb = 72 mhz) tbd tbd tbd ns t d(mdio) mdio write data valid time tbd tbd tbd ns t su(mdio) read data setup time tbd tbd tbd ns t h(mdio) read data hold time tbd tbd tbd ns eth_mdc eth_mdio(o) eth_mdio(i) t mdc t d(mdio) t su (mdio) t h(mdio) a i15666c electrical characteristics stm32f405xx, STM32F407XX 106/154 doc id 022152 rev 1 ta bl e 6 2 gives the list of ethernet mac signals for the rmii and figure 39 shows the corresponding timing diagram. figure 39. ethernet rmii timing diagram ta bl e 6 3 gives the list of ethernet mac signals for mii and figure 39 shows the corresponding timing diagram. figure 40. ethernet mii timing diagram table 62. dynamics characteristics: ethernet mac signals for rmii (1) 1. tbd stands for ?to be defined?. symbol rating min typ max unit t su(rxd) receive data setup time tbd tbd tbd ns t ih(rxd) receive data hold time tbd tbd tbd ns t su(crs) carrier sense set-up time tbd tbd tbd ns t ih(crs) carrier sense hold time tbd tbd tbd ns t d(txen) transmit enable valid delay time 0 9.6 21.9 ns t d(txd) transmit data valid delay time 0 9.9 21 ns rmii_ref_clk rmii_tx_en rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv t d(txen) t d(txd) t su(rxd) t su(crs) t ih(rxd) t ih(crs) ai15667 mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er t d(txen) t d(txd) t su(rxd) t su(er) t su(dv) t ih(rxd) t ih(er) t ih(dv) ai15668 mii_tx_clk mii_tx_en mii_txd[3:0] stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 107/154 can (controller area network) interface refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (cantx and canrx). 5.3.20 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 6 4 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 1 0 . table 63. dynamics characteristics: ethernet mac signals for mii (1) 1. tbd stands for ?to be defined?. symbol rating min typ max unit t su(rxd) receive data setup time tbd tbd tbd ns t ih(rxd) receive data hold time tbd tbd tbd ns t su(dv) data valid setup time tbd tbd tbd ns t ih(dv) data valid hold time tbd tbd tbd ns t su(er) error setup time tbd tbd tbd ns t ih(er) error hold time tbd tbd tbd ns t d(txen) transmit enable valid delay time 13.4 15.5 17.7 ns t d(txd) transmit data valid delay time 12.9 16.1 19.4 ns table 64. adc characteristics (1) symbol parameter conditions min typ max unit v dda power supply 1.8 (2) -3.6v v ref+ (3) positive reference voltage 1.8 (2)(4) -v dda v f adc adc clock frequency v dda = 1.8 (2) to 2.4 v 0.6 - tbd mhz v dda = 2.4 to 3.6 v 0.6 - tbd mhz f trig (5) external trigger frequency f adc = 36 mhz - - tbd khz --171/f adc v ain conversion voltage range (6) 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (5) external input impedance see equation 1 for details --50k r adc (5)(7) sampling switch resistance 1.5 - 6 k c adc (5) internal sample and hold capacitor 4-tbdpf t lat (5) injection trigger conversion latency f adc = 36 mhz - - 0.100 s --3 (8) 1/f adc t latr (5) regular trigger conversion latency f adc = 36 mhz - - 0.067 s --2 (8) 1/f adc electrical characteristics stm32f405xx, STM32F407XX 108/154 doc id 022152 rev 1 t s (5) sampling time f adc = 36 mhz 0.100 - 16 s 3 - 416 1/f adc t stab (5) power-up time - 2 3 s t conv (5) total conversion time (including sampling time) f adc = 36 mhz 12-bit resolution 0.416 - 12.95 s f adc = 36 mhz 10-bit resolution 0.360 - 12.89 s f adc = 36 mhz 8-bit resolution 0.305 - 12.84 s f adc = 36 mhz 6-bit resolution 0.250 - 12.79 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc f s (5) sampling rate (f adc = 36 mhz) 12-bit resolution single adc --2.4msps 12-bit resolution interleave dual adc mode --4.8msps 12-bit resolution interleave triple adc mode --7.2msps i vref+ (5) adc v ref dc current consumption in conversion mode f adc = 36 mhz 3 sampling time 12-bit resolution - 300 500 a f adc = 36 mhz 480 sampling time 12-bit resolution --tbda i dda (5) adc vdda dc current consumption in conversion mode f adc = 36 mhz 3 sampling time 12-bit resolution -1.61.8 ma f adc = 36 mhz 480 sampling time 12-bit resolution --tbd 1. tbd stands for ?to be defined?. 2. if pdr_on is set to v ss , this value can be lowered to 1.7 v when the dev ice operates in a reduced temperature range (0 to 70 c). 3. v dda -v ref+ < 1.2 v. 4. it is recommended to maintain the voltage difference between v ref+ and v dda below 1.8 v. 5. based on characterization, not tested in production. 6. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 7. r adc maximum value is given for v dd =1.8 v, and minimum value for v dd =3.3 v. 8. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 64 . table 64. adc characteristics (1) (continued) symbol parameter conditions min typ max unit stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 109/154 equation 1: r ain max formula the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. a note: adc accuracy vs. negative injection current: injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. any positive injectio n current within the limits specified for i inj(pin) and i inj(pin) in section 5.3.16 does not affect the adc accuracy. table 65. adc accuracy (1)(2) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. 2. tbd stands for ?to be defined?. symbol parameter test conditions typ max (3) 3. based on characterization , not tested in production. unit et total unadjusted error f pclk2 = 84 mhz, f adc = 36 mhz, r ain < 10 k , v dda = 1.8 (4) to 3.6 v 4. if pdr_on is set to v ss , this value can be lowered to 1.7 v when the device oper ates in a reduced temperature range (0 to 70 c). tbd tbd lsb eo offset error tbd tbd eg gain error tbd tbd ed differential linearity error tbd tbd el integral linearity error tbd tbd r ain k0.5 ? () f adc c adc 2 n 2 + () ln -------------------------------------------------------------- r adc ? = electrical characteristics stm32f405xx, STM32F407XX 110/154 doc id 022152 rev 1 figure 41. adc accura cy characteristics 1. see also ta b l e 6 5 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum dev iation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual tr ansition and the end point correlation line. figure 42. typical connection diagram using the adc 1. refer to ta b l e 6 4 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion ac curacy. to remedy this, f adc should be reduced. % / % ' , 3 " ) $ % ! , % 4 % $ % , 6 $ $ ! 6 3 3 ! a i c 6 2 % & o r d e p e n d i n g o n p a c k a g e = 6 $ $ ! ; , 3 " ) $ % ! , a i175 3 4 s tm 3 2f v dd ainx i l 1 a 0.6 v v t r ain (1) c p a r as itic v ain 0.6 v v t r adc (1) c adc (1) 12- b it converter sa mple a nd hold adc converter stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 111/154 general pcb design guidelines power supply decoupling should be performed as shown in figure 43 or figure 44 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 43. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176. v ref+ is also available on lqfp100, lqfp144, and lqfp176. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . figure 44. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176. v ref+ is also available on lqfp100, lqfp144, and lqfp176. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . v ref+ s tm 3 2f v dda v ss a /v ref- 1 f // 10 nf 1 f // 10 nf a i175 3 5 ( s ee note 1) ( s ee note 1) v ref+ /v dda s tm 3 2f 1 f // 10 nf v ref? /v ss a a i175 3 6 ( s ee note 1) ( s ee note 1) electrical characteristics stm32f405xx, STM32F407XX 112/154 doc id 022152 rev 1 5.3.21 temperature sen sor characteristics 5.3.22 v bat monitoring characteristics 5.3.23 embedded reference voltage the parameters given in ta bl e 6 8 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 0 . table 66. ts characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 mv/c v 25 (1) voltage at 25 c - 0.76 v t start (2) startup time - 6 10 s t s_temp (3)(2) adc sampling time when reading the temperature (1 c accuracy) 10 - - s 1. based on characterization, not tested in production. 2. guaranteed by design, not tested in production. 3. shortest sampling time can be determined in the application by multiple iterations. table 67. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 2 - er (1) error on q ?1 - +1 % t s_vbat (2)(2) adc sampling time when reading the v bat 1 mv accuracy 5- -s 1. guaranteed by design, not tested in production. 2. shortest sampling time can be determined in the application by multiple iterations. table 68. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage 10 - - s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3 v - 3 5 mv t coeff (2) temperature coefficient - 30 50 ppm/c t start (2) startup time - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design, not tested in production. stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 113/154 5.3.24 dac electrical characteristics table 69. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 1.8 (1) -3.6 v v ref+ reference supply voltage 1.8 (1) -3.6vv ref+ v dda v ssa ground 0 - 0 v r load (2) resistive load with buffer on 5 - - k r o (2) impedance output with buffer off -- 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (2) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.8 v dac_out max (2) higher dac_out voltage with buffer on --v dda ? 0.2 v dac_out min (2) lower dac_out voltage with buffer off -0.5 - mv it gives the maximum output excursion of the dac. dac_out max (2) higher dac_out voltage with buffer off --v ref+ ? 1lsb v i vref+ (3) dac dc v ref current consumption in quiescent mode (standby mode) - 170 240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs -50 75 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda (3) dac dc vdda current consumption in quiescent mode (standby mode) - 280 380 a with no load, middle code (0x800) on the inputs - 475 625 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (3) differential non linearity difference between two consecutive code-1lsb) -- 0.5 lsb given for the dac in 10-bit configuration. -- 2 lsb given for the dac in 12-bit configuration. electrical characteristics stm32f405xx, STM32F407XX 114/154 doc id 022152 rev 1 inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) -- 1 lsb given for the dac in 10-bit configuration. -- 4 lsb given for the dac in 12-bit configuration. offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) -- 10 mv given for the dac in 12-bit configuration -- 3 lsb given for the dac in 10-bit at v ref+ = 3.6 v -- 12lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (3) gain error - - 0.5 % given for the dac in 12-bit configuration t settling (3) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 4lsb -3 6 s c load 50 pf, r load 5 k thd (3) total harmonic distortion buffer on -- - db c load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1 ms/s c load 50 pf, r load 5 k t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) -6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement) - ?67 ?40 db no r load , c load = 50 pf 1. if pdr_on is set to v ss , this value can be lowered to 1.7 v when the devic e operates in a reduced temperature range (0 to 70 c). 2. guaranteed by design, not tested in production. 3. guaranteed by characterizati on, not tested in production. table 69. dac characteristics (continued) symbol parameter min typ max unit comments stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 115/154 figure 45. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157 electrical characteristics stm32f405xx, STM32F407XX 116/154 doc id 022152 rev 1 5.3.25 fsmc characteristics asynchronous waveforms and timings figure 46 through figure 49 represent asynchronous waveforms and ta b l e 7 0 through ta bl e 7 3 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: addresssetuptime = 0 addressholdtime = 1 datasetuptime = 1 figure 46. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 70. asynchronous non-multiplexed sram/psram/nor read timings (1)(2)(3) symbol parameter min max unit t w(ne) fsmc_ne low time tbd tbd ns t v(noe_ne) fsmc_nex low to fsmc_noe low tbd tbd ns t w(noe) fsmc_noe low time tbd tbd ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time tbd - ns t v(a_ne) fsmc_nex low to fsmc_a valid - tbd ns t h(a_noe) address hold time after fsmc_noe high tbd - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0 ns $ a t a & 3 - # ? . % & 3 - # ? . " , ; = & 3 - # ? $ ; = t v " , ? . % t h $ a t a ? . % & 3 - # ? . / % ! d d r e s s & 3 - # ? ! ; = t v ! ? . % & 3 - # ? . 7 % t s u $ a t a ? . % t w . % a i c w . / % t t v . / % ? . % t h . % ? . / % t h $ a t a ? . / % t h ! ? . / % t h " , ? . / % t s u $ a t a ? . / % & 3 - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 117/154 figure 47. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. t h(bl_noe) fsmc_bl hold time after fsmc_noe high tbd - ns t su(data_ne) data to fsmc_nex high setup time tbd - ns t su(data_noe) data to fsmc_noex high setup time tbd - ns t h(data_noe) data hold time after fsmc_noe high tbd - ns t h(data_ne) data hold time after fsmc_nex high tbd - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - tbd ns t w(nadv) fsmc_nadv low time - tbd ns 1. c l = 15 pf. 2. preliminary values. 3. tbd stands for ?to be defined?. table 71. asynchronous non-multiplexed sram/psram/nor write timings (1)(2)(3) symbol parameter min max unit t w(ne) fsmc_ne low time tbd tbd ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low tbd tbd ns t w(nwe) fsmc_nwe low time tbd tbd ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time tbd - ns table 70. asynchronous non-multiplexed sram/psram/nor read timings (1)(2)(3) symbol parameter min max unit nbl data fsmc_nex fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:0] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(data_ne) t w(ne) ai14990 fsmc_nadv (1) t v(nadv_ne) t w(nadv) electrical characteristics stm32f405xx, STM32F407XX 118/154 doc id 022152 rev 1 figure 48. asynchronous multiplexed psram/nor read waveforms t v(a_ne) fsmc_nex low to fsmc_a valid - tbd ns t h(a_nwe) address hold time after fsmc_nwe high tbd - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - tbd ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high tbd - ns t v(data_ne) fsmc_nex low to data valid - tbd ns t h(data_nwe) data hold time after fsmc_nwe high tbd - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - tbd ns t w(nadv) fsmc_nadv low time - tbd ns 1. c l = 15 pf. 2. preliminary values. 3. tbd stands for ?to be defined?. table 71. asynchronous non-multiplexed sram/psram/nor write timings (1)(2)(3) symbol parameter min max unit nbl data fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_ne) address fsmc_a[25:16] t v(a_ne) fsmc_nwe t v(a_ne) ai14892b address fsmc_nadv t v(nadv_ne) t w(nadv) t su(data_ne) t h(ad_nadv) fsmc_ne fsmc_noe t w(ne) t w(noe) t v(noe_ne) t h(ne_noe) t h(a_noe) t h(bl_noe) t su(data_noe) t h(data_noe) stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 119/154 table 72. asynchronous multiplexed psram/nor read timings (1)(2)(3) 1. c l = 15 pf. 2. preliminary values. 3. tbd stands for ?to be defined?. symbol parameter min max unit t w(ne) fsmc_ne low time tbd tbd ns t v(noe_ne) fsmc_nex low to fsmc_noe low tbd tbd ns t w(noe) fsmc_noe low time tbd tbd ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time tbd - ns t v(a_ne) fsmc_nex low to fsmc_a valid - tbd ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low tbd tbd ns t w(nadv) fsmc_nadv low time tbd tbd ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high tbd - ns t h(a_noe) address hold time after fsmc_noe high tbd - ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high tbd - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - tbd ns t su(data_ne) data to fsmc_nex high setup time tbd - ns t su(data_noe) data to fsmc_noe high setup time tbd - ns t h(data_ne) data hold time after fsmc_nex high tbd - ns t h(data_noe) data hold time after fsmc_noe high tbd - ns electrical characteristics stm32f405xx, STM32F407XX 120/154 doc id 022152 rev 1 figure 49. asynchronous multiplexed psram/nor write waveforms table 73. asynchronous multiplexed psram/nor write timings (1)(2)(3) 1. c l = 15 pf. 2. preliminary values. 3. tbd stands for ?to be defined?. symbol parameter min max unit t w(ne) fsmc_ne low time tbd tbd ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low tbd tbd ns t w(nwe) fsmc_nwe low time tbd tbd ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time tbd - ns t v(a_ne) fsmc_nex low to fsmc_a valid - tbd ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low tbd tbd ns t w(nadv) fsmc_nadv low time tbd tbd ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high tbd - ns t h(a_nwe) address hold time after fsmc_nwe high tbd - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - tbd ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high tbd - ns t v(data_nadv) fsmc_nadv high to data valid - tbd ns t h(data_nwe) data hold time after fsmc_nwe high tbd - ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:16] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(a_ne) t w(ne) ai14891b address fsmc_nadv t v(nadv_ne) t w(nadv) t v(data_nadv) t h(ad_nadv) stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 121/154 synchronous waveforms and timings figure 50 through figure 53 represent synchronous waveforms and ta bl e 7 5 through ta bl e 7 7 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: burstaccessmode = fsmc_burstaccessmode_enable; memorytype = fsmc_memorytype_cram; writeburst = fsmc_writeburst_enable; clkdivision = 1; (0 is not supported, see the stm32f20xxx/21xxx reference manual) datalatency = 1 for nor flash; datalatency = 0 for psram figure 50. synchronous multiplexed nor/psram read timings & 3 - # ? # , + & 3 - # ? . % x & 3 - # ? . ! $ 6 & 3 - # ? ! ; = & 3 - # ? . / % & 3 - # ? ! $ ; = ! $ ; = $ $ & 3 - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b & 3 - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + , . % x ( t d # , + , . ! $ 6 , t d # , + , ! 6 t d # , + , . ! $ 6 ( t d # , + , ! ) 6 t d # , + , . / % , t d # , + , . / % ( t d # , + , ! $ 6 t d # , + , ! $ ) 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 a i g electrical characteristics stm32f405xx, STM32F407XX 122/154 doc id 022152 rev 1 table 74. synchronous multiplexed nor/psram read timings (1)(2)(3) 1. c l = 15 pf. 2. preliminary values. 3. tbd stands for ?to be defined?. symbol parameter min max unit t w(clk) fsmc_clk period 16.7 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - tbd ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) tbd - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - tbd ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high tbd - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) - tbd ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) tbd - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - tbd ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high tbd - ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid - tbd ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid tbd - ns t su(adv-clkh) fsmc_a/d[15:0] valid data before fsmc_clk high tbd - ns t h(clkh-adv) fsmc_a/d[15:0] valid data after fsmc_clk high tbd - ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high tbd - ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high tbd - ns stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 123/154 figure 51. synchronous multiplexed psram write timings & 3 - # ? # , + & 3 - # ? . % x & 3 - # ? . ! $ 6 & 3 - # ? ! ; = & 3 - # ? . 7 % & 3 - # ? ! $ ; = ! $ ; = $ $ & 3 - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + , . % x ( t d # , + , . ! $ 6 , t d # , + , ! 6 t d # , + , . ! $ 6 ( t d # , + , ! ) 6 t d # , + , . 7 % ( t d # , + , . 7 % , t d # , + , . " , ( t d # , + , ! $ 6 t d # , + , ! $ ) 6 t d # , + , $ a t a t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 a i f t d # , + , $ a t a & 3 - # ? . " , electrical characteristics stm32f405xx, STM32F407XX 124/154 doc id 022152 rev 1 table 75. synchronous multiplexed psram write timings (1)(2) 1. c l = 15 pf. 2. preliminary values. symbol parameter min max unit t w(clk) fsmc_clk period tbd - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - tbd ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) tbd - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - tbd ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high tbd - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) - tbd ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) tbd - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - tbd ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high tbd - ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid - tbd ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid tbd - ns t d(clkl-data) fsmc_a/d[15:0] valid after fsmc_clk low - tbd ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high tbd - ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high tbd - ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high tbd - ns stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 125/154 figure 52. synchronous non-multiplexed nor/psram read timings table 76. synchronous non-multiplexed nor/psram read timings (1)(2)(3) 1. c l = 15 pf. 2. preliminary values. 3. tbd stands for ?to be defined?. symbol parameter min max unit t w(clk) fsmc_clk period tbd - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - tbd ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) tbd - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - tbd ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high tbd - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 0...25) - tbd ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 0...25) tbd - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - tbd ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high tbd - ns t su(dv-clkh) fsmc_d[15:0] valid data bef ore fsmc_clk high tbd - ns t h(clkh-dv) fsmc_d[15:0] valid data after fsmc_clk high tbd - ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_smclk high tbd - ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high tbd - ns & 3 - # ? # , + & 3 - # ? . % x & 3 - # ? ! ; = & 3 - # ? . / % & 3 - # ? $ ; = $ $ & 3 - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b & 3 - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + , . % x ( t d # , + , ! 6 t d # , + , ! ) 6 t d # , + , . / % , t d # , + , . / % ( t s u $ 6 # , + ( t h # , + ( $ 6 t s u $ 6 # , + ( t h # , + ( $ 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 a i f & 3 - # ? . ! $ 6 t d # , + , . ! $ 6 , t d # , + , . ! $ 6 ( electrical characteristics stm32f405xx, STM32F407XX 126/154 doc id 022152 rev 1 figure 53. synchronous non-multiplexed psram write timings table 77. synchronous non-multiplexed psram write timings (1)(2)(3) 1. c l = 15 pf. 2. preliminary values. 3. tbd stands for ?to be defined?. symbol parameter min max unit t w(clk) fsmc_clk period tbd - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - tbd ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) tbd - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - tbd ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high tbd - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) - tbd ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) tbd ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - tbd ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high tbd - ns t d(clkl-data) fsmc_d[15:0] valid data after fsmc_clk low - tbd ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high tbd - ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high tbd - ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high tbd - ns & 3 - # ? # , + & 3 - # ? . % x & 3 - # ? ! ; = & 3 - # ? . 7 % & 3 - # ? $ ; = $ $ & 3 - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + , . % x ( t d # , + , ! 6 t d # , + , ! ) 6 t d # , + , . 7 % ( t d # , + , . 7 % , t d # , + , $ a t a t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 a i g & 3 - # ? . ! $ 6 t d # , + , . ! $ 6 , t d # , + , . ! $ 6 ( t d # , + , $ a t a & 3 - # ? . " , t d # , + , . " , ( stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 127/154 pc card/compactflash controller waveforms and timings figure 54 through figure 59 represent synchronous waveforms and ta bl e 7 8 provides the corresponding timings. the results shown in th is table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x04; com.fsmc_waitsetuptime = 0x07; com.fsmc_holdsetuptime = 0x04; com.fsmc_hizsetuptime = 0x00; att.fsmc_setuptime = 0x04; att.fsmc_waitsetuptime = 0x07; att.fsmc_holdsetuptime = 0x04; att.fsmc_hizsetuptime = 0x00; io.fsmc_setuptime = 0x04; io.fsmc_waitsetuptime = 0x07; io.fsmc_holdsetuptime = 0x04; io.fsmc_hizsetuptime = 0x00; tclrsetuptime = 0; tarsetuptime = 0; figure 54. pc card/compactflash controller waveforms for common memory read access 1. fsmc_nce4_2 remains high (inactive during 8-bit access. fsmc_nwe t w(noe) fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 (1) fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nce4_1-noe) t su(d-noe) t h(noe-d) t v(ncex-a) t d(nreg-ncex) t d(niord-ncex) t h(ncex-ai) t h(ncex-nreg) t h(ncex-niord) t h(ncex- niowr ) ai14895b electrical characteristics stm32f405xx, STM32F407XX 128/154 doc id 022152 rev 1 figure 55. pc card/compactflash controller waveforms for common memory write access t d(nce4_1-nwe) t w(nwe) t h(nwe-d) t v(nce4_1-a) t d(nreg-nce4_1) t d(niord-nce4_1) t h(nce4_1-ai) memxhiz =1 t v(nwe-d) t h(nce4_1-nreg) t h(nce4_1-niord) t h(nce4_1-niowr) ai14896b fsmc_nwe fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) t d(d-nwe) fsmc_nce4_2 high stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 129/154 figure 56. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). t d(nce4_1-noe) t w(noe) t su(d-noe) t h(noe-d) t v(nce4_1-a) t h(nce4_1-ai) t d(nreg-nce4_1) t h(nce4_1-nreg) ai14897b fsmc_nwe fsmc_noe fsmc_d[15:0] (1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(noe-nce4_1) high electrical characteristics stm32f405xx, STM32F407XX 130/154 doc id 022152 rev 1 figure 57. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are driven (bits 8...15 remains hi-z). figure 58. pc card/compactflash controller waveforms for i/o space read access t w(nwe) t v(nce4_1-a) t d(nreg-nce4_1) t h(nce4_1-ai) t h(nce4_1-nreg) t v(nwe-d) ai14898b fsmc_nwe fsmc_noe fsmc_d[7:0](1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) high t d(nce4_1-nwe) t d(niord-nce4_1) t w(niord) t su(d-niord) t d(niord-d) t v(ncex-a) t h(nce4_1-ai) ai14899b fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 131/154 figure 59. pc card/compactflash controller waveforms for i/o space write access t d . # % ? . ) / 7 2 t w . ) / 7 2 t v . # % x ! t h . # % ? ! ) t h . ) / 7 2 $ ! 4 4 x ( ) : t v . ) / 7 2 $ a i c & 3 - # ? . 7 % & 3 - # ? . / % & 3 - # ? $ ; = & 3 - # ? ! ; = & 3 - # ? . # % ? & 3 - # ? . # % ? & 3 - # ? . 2 % ' & 3 - # ? . ) / 7 2 & 3 - # ? . ) / 2 $ table 78. switching characteristics for pc card/cf read and write cycles (1)(2)(3) symbol parameter min max unit t v(ncex-a) t v(nce4_1-a) fsmc_ncex low (x = 4_1/4_2) to fsmc_ay valid (y = 0...10) fsmc_nce4_1 low (x = 4_1/4_2) to fsmc_ay valid (y = 0...10) -tbd ns t h(ncex-ai) t h(nce4_1-ai) fsmc_ncex high (x = 4_1/4_2) to fsmc_ax invalid (x = 0...10) fsmc_nce4_1 high (x = 4_1/4_2) to fsmc_ax invalid (x = 0...10) tbd ns t d(nreg-ncex) t d(nreg-nce4_1) fsmc_ncex low to fsmc_nreg valid fsmc_nce4_1 low to fsmc_nreg valid -tbd ns t h(ncex-nreg) t h(nce4_1-nreg) fsmc_ncex high to fsmc_nreg invalid fsmc_nce4_1 high to fsmc_nreg invalid tbd - ns t d(nce4_1-noe) fsmc_nce4_1 low to fsmc_noe low - tbd ns t w(noe) fsmc_noe low width tbd tbd ns t d(noe-nce4_1 fsmc_noe high to fsmc_nce4_1 high tbd - ns t su(d-noe) fsmc_d[15:0] valid data before fsmc_noe high tbd - ns t h(noe-d) fsmc_d[15:0] valid data after fsmc_noe high tbd - ns t w(nwe) fsmc_nwe low width tbd tbd ns t d(nwe-nce4_1) fsmc_nwe high to fsmc_nce4_1 high tbd - ns t d(nce4_1-nwe) fsmc_nce4_1 low to fsmc_nwe low - tbd ns t v(nwe-d) fsmc_nwe low to fsmc_d[15:0] valid - tbd ns t h(nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid tbd - ns t d(d-nwe) fsmc_d[15:0] valid before fsmc_nwe high tbd - ns electrical characteristics stm32f405xx, STM32F407XX 132/154 doc id 022152 rev 1 nand controller waveforms and timings figure 60 through figure 63 represent synchronous waveforms and ta bl e 7 9 provides the corresponding timings. the results shown in th is table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x01; com.fsmc_waitsetuptime = 0x03; com.fsmc_holdsetuptime = 0x02; com.fsmc_hizsetuptime = 0x01; att.fsmc_setuptime = 0x01; att.fsmc_waitsetuptime = 0x03; att.fsmc_holdsetuptime = 0x02; att.fsmc_hizsetuptime = 0x01; bank = fsmc_bank_nand; memorydatawidth = fsmc_memorydatawidth_16b; ecc = fsmc_ecc_enable; eccpagesize = fsmc_eccpagesize_512bytes; tclrsetuptime = 0; tarsetuptime = 0; t w(niowr) fsmc_niowr low width tbd - ns t v(niowr-d) fsmc_niowr low to fsmc_d[15:0] valid - tbd ns t h(niowr-d) fsmc_niowr high to fsmc_d[15:0] invalid tbd - ns t d(nce4_1-niowr) fsmc_nce4_1 low to fsmc_niowr valid - tbd ns t h(ncex-niowr) t h(nce4_1-niowr) fsmc_ncex high to fsmc_niowr invalid fsmc_nce4_1 high to fsmc_niowr invalid tbd - ns t d(niord-ncex) t d(niord-nce4_1) fsmc_ncex low to fsmc_niord valid fsmc_nce4_1 low to fsmc_niord valid -tbd ns t h(ncex-niord) t h(nce4_1-niord) fsmc_ncex high to fsmc_niord invalid fsmc_nce4_1 high to fsmc_niord invalid tbd - ns t su(d-niord) fsmc_d[15:0] valid before fsmc_niord high tbd - ns t d(niord-d) fsmc_d[15:0] valid after fsmc_niord high tbd - ns t w(niord) fsmc_niord low width tbd - ns 1. c l = 15 pf. 2. based on characterization, not tested in production. 3. tbd stands for ?to be defined?. table 78. switching characteristics for pc card/cf read and write cycles (1)(2)(3) (continued) symbol parameter min max unit stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 133/154 figure 60. nand controller waveforms for read access figure 61. nand controller waveforms for write access & 3 - # ? . 7 % & 3 - # ? . / % . 2 % & 3 - # ? $ ; = t s u $ . / % t h . / % $ a i c ! , % & 3 - # ? ! # , % & 3 - # ? ! & 3 - # ? . # % x t d ! , % . / % t h . / % ! , % t h . 7 % $ t v . 7 % $ a i c & 3 - # ? . 7 % & 3 - # ? . / % . 2 % & 3 - # ? $ ; = ! , % & 3 - # ? ! # , % & 3 - # ? ! & 3 - # ? . # % x t d ! , % . 7 % t h . 7 % ! , % electrical characteristics stm32f405xx, STM32F407XX 134/154 doc id 022152 rev 1 figure 62. nand controller waveforms for common memo ry read access figure 63. nand controller waveforms for common memory write access table 79. switching characteristics fo r nand flash read and write cycles (1)(2) symbol parameter min max unit t d(d-nwe) (3) fsmc_d[15:0] valid before fsmc_nwe high tbd - ns t w(noe) (3) fsmc_noe low width tbd tbd ns t su(d-noe) (3) fsmc_d[15:0] valid data before fsmc_noe high tbd - ns t h(noe-d) (3) fsmc_d[15:0] valid data after fsmc_noe high tbd - ns t w(nwe) (3) fsmc_nwe low width tbd tbd ns t v(nwe-d) (3) fsmc_nwe low to fsmc_d[15:0] valid - tbd ns t h(nwe-d) (3) fsmc_nwe high to fsmc_d[15:0] invalid tbd - ns & 3 - # ? . 7 % & 3 - # ? . / % & 3 - # ? $ ; = t w . / % t s u $ . / % t h . / % $ a i c ! , % & 3 - # ? ! # , % & 3 - # ? ! & 3 - # ? . # % x t d ! , % . / % t h . / % ! , % t w . 7 % t h . 7 % $ t v . 7 % $ a i c & 3 - # ? . 7 % & 3 - # ? . / % & 3 - # ? $ ; = t d $ . 7 % ! , % & 3 - # ? ! # , % & 3 - # ? ! & 3 - # ? . # % x t d ! , % . / % t h . / % ! , % stm32f405xx, STM32F407XX electrical characteristics doc id 022152 rev 1 135/154 5.3.26 camera interface (dcmi) timing specifications 5.3.27 sd/sdio mmc ca rd host interface (sdio) characteristics unless otherwise specified, the parameters given in ta bl e 8 1 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta b l e 1 0 . refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (d[7:0], cmd, ck). figure 64. sdio high-speed mode t d(ale-nwe) (4) fsmc_ale valid before fsmc_nwe low - tbd ns t h(nwe-ale) (4) fsmc_nwe high to fsmc_ale invalid tbd - ns t d(ale-noe) (4) fsmc_ale valid before fsmc_noe low - tbd ns t h(noe-ale) (4) fsmc_nwe high to fsmc_ale invalid tbd - ns 1. c l = 15 pf. 2. tbd stands for ?to be defined?. 3. based on characterization , not tested in production. 4. guaranteed by design, not tested in production. table 79. switching characteristics fo r nand flash read and write cycles (1)(2) symbol parameter min max unit table 80. dcmi characteristics symbol parameter conditions min max unit frequency ratio dcmi_pixclk/ f hclk (1) 0.4 1. maximum value of dcmi_pixclk = 54 mhz. t w(ckh) ck d, cmd (output) d, cmd (input) t c t w(ckl) t ov t oh t isu t ih t f t r ai14887 electrical characteristics stm32f405xx, STM32F407XX 136/154 doc id 022152 rev 1 figure 65. sd default mode 5.3.28 rtc characteristics table 81. sd / mmc characteristics (1) 1. tbd stands for ?to be defined?. symbol parameter conditions min max unit f pp clock frequency in data transfer mode c l 30 pf tbd tbd mhz - sdio_ck/f pclk2 frequency ratio - - tbd - t w(ckl) clock low time, f pp = 16 mhz c l 30 pf tbd - ns t w(ckh) clock high time, f pp = 16 mhz c l 30 pf tbd - t r clock rise time c l 30 pf - tbd t f clock fall time c l 30 pf - tbd cmd, d inputs (referenced to ck) t isu input setup time c l 30 pf tbd - ns t ih input hold time c l 30 pf tbd - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time c l 30 pf - tbd ns t oh output hold time c l 30 pf tbd - cmd, d outputs (referenced to ck) in sd default mode (2) 2. refer to sdio_clkcr, the sdi clock control register to control the ck output. t ovd output valid default time c l 30 pf - tbd ns t ohd output hold default time c l 30 pf tbd - ck d, cmd (output) t ovd t ohd ai14888 table 82. rtc characteristics symbol parameter conditions min max unit - f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4-- stm32f405xx, STM32F407XX package characteristics doc id 022152 rev 1 137/154 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. package characteristics stm32f405xx, STM32F407XX 138/154 doc id 022152 rev 1 figure 66. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline (1) figure 67. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. a a2 a1 c l1 l e e1 d d1 e b ai14398b 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 83. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 12.000 0.4724 d1 10.000 0.3937 e 12.000 0.4724 e1 10.000 0.3937 e 0.500 0.0197 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits. stm32f405xx, STM32F407XX package characteristics doc id 022152 rev 1 139/154 figure 68. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline (1) figure 69. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 table 84. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 12.000 0.4724 e 15.80v 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 12.000 0.4724 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f405xx, STM32F407XX 140/154 doc id 022152 rev 1 figure 70. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline (1) figure 71. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 a 1 36 37 72 73 108 109 144 table 85. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.874 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 17.500 0.689 e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 17.500 0.6890 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. stm32f405xx, STM32F407XX package characteristics doc id 022152 rev 1 141/154 figure 72. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline 1. drawing is not to scale. s e a ting pl a ne c a2 a4 a 3 c ddd a1 a a b e f d f e e r eee m cab c fff (176 ba ll s ) ? b m ? ? a0e7_me b a ll a1 a 15 1 table 86. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data symbol millimeters inches (1) min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.002 0.0031 0.0043 a2 0.400 0.450 0.500 0. 0157 0.0177 0.0197 a3 0.130 0.0051 a4 0.270 0.320 0.370 0. 0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 9.950 10.000 10.050 0.3740 0.3937 0.3957 e 9.950 10.000 10.050 0.3740 0.3937 0.3957 e 0.600 0.650 0.700 0.0236 0.0256 0.0276 f 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f405xx, STM32F407XX 142/154 doc id 022152 rev 1 figure 73. lqfp176 24 x 24 mm, 144-pin low-profile quad flat package outline 1. drawing is not to scale. ccc c s e a ting pl a ne c aa2 a1 c 0.25 mm g au ge pl a ne hd d a1 l l1 k 8 9 88 ehe 45 44 e 1 176 pin 1 identific a tion b 1 33 1 3 2 1t_me zd ze table 87. lqfp176, 24 x 24 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 a2 1.350 1.450 0.0531 0.0060 b 0.170 0.270 0.0067 0.0106 c 0.090 0.200 0.0035 0.0079 d 23.900 24.100 0.9409 0.9488 e 23.900 24.100 0.9409 0.9488 e 0.500 0.0197 hd 25.900 26.100 1.0200 1.0276 he 25.900 26.100 1.0200 1.0276 l 0.450 0.750 0.0177 0.0295 l1 1.000 0.0394 zd 1.250 0.0492 ze 1.250 0.0492 ccc 0.080 0.0031 k0 7 0 7 1. values in inches are converted from mm and rounded to 4 decimal digits. stm32f405xx, STM32F407XX package characteristics doc id 022152 rev 1 143/154 6.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: t a max is the maximum ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org. table 88. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp 64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient lqfp 144 - 20 20 mm / 0.5 mm pitch 40 thermal resistance junction-ambient ufbga176 - 10 10 mm / 0.5 mm pitch 39 part numbering stm32f405xx, STM32F407XX 144/154 doc id 022152 rev 1 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 89. ordering information scheme example: stm32 f 405 r e t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 405 = stm32f40x, connectivity, usb otg fs/hs, 407= stm32f40x, connectivity, usb otg fs/hs, camera interface, ethernet pin count r = 64 pins or 66 pins v = 100 pins z = 144 pins i = 176 pins flash memory size c = 256 kbytes of flash memory e = 512 kbytes of flash memory f = 768 kbytes of flash memory g = 1024 kbytes of flash memory package t = lqfp h = ufbga temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and reel stm32f405xx, STM32F407XX application block diagrams doc id 022152 rev 1 145/154 appendix a application block diagrams a.1 main applications versus package ta bl e 9 0 gives examples of configurations for each package. table 90. main applications versus package for STM32F407XX microcontrollers (1) 64 pins 100 pins 144 pins 176 pins config 1 config 2 config 3 config 1 config 2 config 3 config 4 config 1 config 2 config 3 config 4 config 1 config 2 usb 1 otg fs xxxxxx - x x x fs xxxxxxxxxxxx usb 2 hs ulpi ---x---xx xx otgfs---x xx xx fs - - - xxxxxxxxxx ethernet mii -----xx xxxx rmii---- xxxxxxxxx spi/i2s2 spi/i2s3 - x - - xxxxxxxxx sdio sdio sdio or dcmi sdio or dcmi - sdio or dcmi sdio or dcmi sdio or dcmi x sdio or dcmi x sdio or dcmi xxx dcmi 8bits data - x x xxx 10bits data - x x xxx 12bits data - x x xxx 14bits data ------- x xxx fsmc nor/ ram muxed - - - xxxxxxxxxx nor/ ram - - - xxxxxx nand - - - x x x* 22 x* 19 xx* 19 x* 22 x* 19 x* 22 x* 22 cf ------- xxxxxx can - xx - xxx - - xx - x 1. x* y : fsmc address limited to ?y?. application block diagrams stm32f405xx, STM32F407XX 146/154 doc id 022152 rev 1 a.2 application exampl e with regulator off figure 74. regulator off/internal reset on 1. this mode is available only on ufbga176 package. figure 75. regulator off/internal reset off 1. this mode is available only on ufbga176 package. " 9 0 ! 3 3 ? 2 % ' 6 # ! 0 ? a i 6 # ! 0 ? 0 ! . 2 3 4 ! p p l i c a t i o n r e s e t s i g n a l o p t i o n a l 6 6 $ $ 0 o w e r d o w n r e s e t r i s e n a f t e r 6 # ! 0 ? 6 # ! 0 ? s t a b i l i z a t i o n " 9 0 ! 3 3 ? 2 % ' 6 # ! 0 ? 6 # ! 0 ? 0 ! 6 6 $ $ 0 o w e r d o w n r e s e t r i s e n b e f o r e 6 # ! 0 ? 6 # ! 0 ? s t a b i l i z a t i o n . 2 3 4 6 $ $ 6 $ $ ! p p l i c a t i o n r e s e t s i g n a l o p t i o n a l 6 # ! 0 ? m o n i t o r i n g % x t r e s e t c o n t r o l l e r a c t i v e w h e n 6 # ! 0 ? 6 0 $ 2 ? / . 0 $ 2 ? / . " 9 0 ! 3 3 ? 2 % ' 6 # ! 0 ? a i 6 # ! 0 ? . 2 3 4 6 6 $ $ 6 $ $ 6 $ $ m o n i t o r i n g % x t r e s e t c o n t r o l l e r a c t i v e w h e n 6 $ $ 6 o r 6 # ! 0 ? 6 # ! 0 ? 6 6 - - o r 6 c a p v 6 $ $ 0 $ 2 ? / . 6 $ $ 0 ! stm32f405xx, STM32F407XX application block diagrams doc id 022152 rev 1 147/154 a.3 usb otg full speed (f s) interface solutions figure 76. usb otg fs peripheral-only connection 1. external voltage regulator only needed when building a v bus powered device. figure 77. usb otg fs host-only connection 1. stmps2141str/stulpi01b needed only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 3 4 - & x x x x 6 t o 6 $ $ 6 o l a t g e r e g u l a t o r 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 ! 0 ! 5 3 " 3 t d " c o n n e c t o r $ - / 3 # ? ) . / 3 # ? / 5 4 - 3 6 3 4 - & x x x x 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 ! 0 ! 5 3 " 3 t d ! c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r / 3 # ? ) . / 3 # ? / 5 4 - 3 6 3 4 - 0 3 3 4 2 3 4 5 , 0 ) " c u r r e n t l i m i t e d p o w e r d i s t r i b u t i o n s w i t c h application block diagrams stm32f405xx, STM32F407XX 148/154 doc id 022152 rev 1 figure 78. otg fs connection dual-role with internal phy 1. external voltage regulator only needed when building a v bus powered device. 2. stmps2141str/stulpi01b needed only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 3. the same application can be developped using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fi fo and to a dedicated dma controller. a.4 usb otg high speed (hs) interface solutions figure 79. usb otg hs peripheral-only connection in fs mode 1. external voltage regulator only needed when building a v bus powered device. 3 4 - & x x x x 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 ! 0 ! 5 3 " m i c r o ! " c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r 6 t o 6 $ $ v o l t a g e r e g u l a t o r 6 $ $ ) $ 0 ! / 3 # ? ) . / 3 # ? / 5 4 - 3 6 3 4 - 0 3 3 4 2 3 4 5 , 0 ) " c u r r e n t l i m i t e d p o w e r d i s t r i b u t i o n s w i t c h 3 4 - & x x x x 6 t o 6 $ $ 6 o l a t g e r e g u l a t o r 6 $ $ 6 " 5 3 $ 0 6 3 3 0 " 0 " 0 " 5 3 " 3 t d " c o n n e c t o r $ - / 3 # ? ) . / 3 # ? / 5 4 - 3 6 stm32f405xx, STM32F407XX application block diagrams doc id 022152 rev 1 149/154 figure 80. usb otg hs host-only connection in fs mode 1. stmps2141str/stulpi01b needed only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. figure 81. otg hs connection dual-role with external phy 1. it is possible to use mco1 or mco2 to save a crys tal. it is however not mandato ry to clock the stm32f40x with a 24 or 26 mhz crystal when using usb hs. the above figure only shows an example of a possible connection. 3 4 - & x x x x 3 4 - 0 3 3 4 2 3 4 5 , 0 ) " c u r r e n t l i m i t e d p o w e r d i s t r i b u t i o n s w i t c h 6 $ $ 6 " 5 3 $ 0 6 3 3 5 3 " 3 t d ! c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r / 3 # ? ) . / 3 # ? / 5 4 - 3 6 0 " 0 " 0 " $ 0 3 4 - & x x x x $ - 6 " 5 3 6 3 3 $ - $ 0 ) $ 5 3 " 5 3 " ( 3 / 4 ' # t r l & 3 0 ( 9 5 , 0 ) ( 3 / 4 ' 0 ( 9 5 , 0 ) ? # , + 5 , 0 ) ? $ ; = 5 , 0 ) ? $ ) 2 5 , 0 ) ? 3 4 0 5 , 0 ) ? . 8 4 n o t c o n n e c t e d c o n n e c t o r - # / o r - # / o r - ( z 8 4 0 , , 8 4 8 ) - 3 6 # a s e o f a n 3 - 3 # w h i c h r e q u i r e d - ( z application block diagrams stm32f405xx, STM32F407XX 150/154 doc id 022152 rev 1 a.5 complete audio player solutions two solutions are offe red, illustrated in figure 82 and figure 83 . figure 82 shows storage media to audio dac/amplifier streaming using a software codec. this solution implements an audio crystal to provide audio class i 2 s accuracy on the master clock (0.5% error maximum, see the serial peripheral interface section in the reference manual for details). figure 82. complete audio player solution 1 figure 83 shows storage media to audio codec/amplifier streaming with sof synchronization of input/output audio streaming using a hardware codec. figure 83. complete audio player solution 2 # o r t e x - & c o r e u p t o - ( z / 4 ' h o s t m o d e 0 ( 9 3 0 ) 3 0 ) ' 0 ) / ) 3 8 4 ! , - ( z o r - ( z 5 3 " - a s s s t o r a g e d e v i c e - - # 3 $ # a r d , # $ t o u c h s c r e e n # o n t r o l b u t t o n s $ ! # ! u d i o a m p l i & i l e 3 y s t e m 0 r o g r a m m e m o r y ! u d i o # / $ % # 5 s e r a p p l i c a t i o n 3 4 - & x x x x - 3 6 # o r t e x - & c o r e u p t o - ( z / 4 ' 0 ( 9 3 0 ) 3 0 ) ' 0 ) / ) 3 5 3 " - a s s s t o r a g e d e v i c e - - # 3 $ # a r d , # $ t o u c h s c r e e n # o n t r o l b u t t o n s ! u d i o a m p l i & i l e 3 y s t e m 0 r o g r a m m e m o r y ! u d i o # / $ % # 5 s e r a p p l i c a t i o n 3 4 - & x x x x - 3 6 3 / & 3 / & s y n c h r o n i z a t i o n o f i n p u t o u t p u t a u d i o s t r e a m i n g 8 4 ! , - ( z o r - ( z stm32f405xx, STM32F407XX application block diagrams doc id 022152 rev 1 151/154 figure 84. audio player solution using pll, plli2s, usb and 1 crystal figure 85. audio pll (plli2s) providing accurate i2s clock / 4 ' - ( z 0 ( 9 8 4 ! , - ( z o r - ( z 3 4 - & x x x x - 3 6 ) 3 a c c u r a c y $ ! # ! u d i o a m p l i - # , + o u t 3 # , + - # / - # / 0 , , ) 3 x . 0 , , x . / 3 # $ i v b y - $ i v b y 0 $ i v b y 1 # o r t e x - & c o r e u p t o - ( z $ i v b y 2 - # , + i n - # / 0 2 % - # / 0 2 % i2 s ctl i2 s _mck = 256 f s audio 11.2 8 96 mhz for 44.1 khz 12.2 88 0 mhz for 4 8 .0 khz i2 s _mck plli2 s /m m=1,2, 3 ,..,64 1 mhz 192 to 4 3 2 mhz n=192,194,..,4 3 2 i2 s com_ck ph as ec vco /n /r clkin ph as e lock detector r=2, 3 ,4,5,6,7 i2 s d=2, 3 ,4.. 129 a i16041 b application block diagrams stm32f405xx, STM32F407XX 152/154 doc id 022152 rev 1 figure 86. master clock (mck) used to drive the external audio dac 1. i2s_sck is the i2s serial clock to the exter nal audio dac (not to be confused with i2s_ck). figure 87. master clock (mck) not used to drive the external audio dac 1. i2s_sck is the i2s serial clock to the exter nal audio dac (not to be confused with i2s_ck). i2 s _ck i2 s controller i2 s _mck = 256 f s audio = 11.2 8 96 mhz for f s audio = 44.1 khz = 12.2 88 0 mhz for f s audio = 4 8 .0 khz /(2 x 16) / 8 /i2 s d f s audio i2 s _ s ck (1) = i2 s _mck/ 8 for 16- b it s tereo for 16- b it s tereo /(2 x 3 2) /4 for 3 2- b it s tereo f s audio 2, 3 ,4,..,129 = i2 s _mck/4 for 3 2- b it s tereo a i16042 i2 s com_ck i2 s controller /(2 x 16) /i2 s d f s audio i2 s _ s ck (1) for 16- b it s tereo /(2 x 3 2) for 3 2- b it s tereo f s audio a i16042 stm32f405xx, STM32F407XX revision history doc id 022152 rev 1 153/154 revision history table 91. document revision history date revision changes 15-sep-2011 1 initial release. stm32f405xx, STM32F407XX 154/154 doc id 022152 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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